View 4506_4951691.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

REJ09B0194-0201
4
4506 Group
User's Manual
RENESAS 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES
Before using this material, please visit our website to confirm that this is the most current document available.
Rev. 2.01 Revision date: Feb 07, 2005
www.renesas.com
Keep safety first in your circuit designs!
1.
Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.
2.
3.
4.
5.
6. 7.
8.
These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http:// www.renesas.com). When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/ or the country of destination is prohibited. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
REVISION HISTORY
Rev. Date Page 1.00 Nov 29, 2002 - First edition issued 2.00 Aug 27, 2004 All pages 1-4 1-5 1-24 1-26 1-30 1-31 1-32 1-40 1-49 1-50 2-40 3-9 3-34 3-39 1-2 2.01 Feb 07, 2005 1-4 1-29 1-48 1-102 1-103 2-32 3-35 3-46
4506 Group User's Manual
Description Summary
Words standardized: On-chip oscillator, A/D converter "Ta=25C" added. ____________ Description of RESET pin revised. Fig.20 : Some description added. Fig.22 : Note 5 added. Some description revised. Fig.25 : "DI" instruction added. Table 11: Revised. Table 15 : Port level revised, Note 5 added. Fig.47 : Some description added. Note on Power Source Voltage added. Table 2.6.1 : Port level revised, Note 5 added. Some description added. Fig.3.3.3 : Some description revised. Note on Power Source Voltage added. Package name revised. Package name revised. * Timer 1 and timer 2 count start timing and count time when operation starts added. * Timer 1 and timer 2 count start timing and count time when operation starts added. Package name revised. Package name revised. (6) Timer 1 and timer 2 count start timing and count time when operation starts added. (6) Timer 1 and timer 2 count start timing and count time when operation starts added. Package outline revised.
BEFORE USING THIS USER'S MANUAL
This user's manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such as hardware design or software development.
1. Organization
q CHAPTER 1 HARDWARE This chapter describes features of the microcomputer and operation of each peripheral function. q CHAPTER 2 APPLICATION This chapter describes usage and application examples of peripheral functions, based mainly on setting examples of related registers. q CHAPTER 3 APPENDIX This chapter includes necessary information for systems development using the microcomputer, such as the electrical characteristics, the list of registers. As for the Mask ROM confirmation form, the ROM programming confirmation form, and the Mark specification form which are to be submitted when ordering, refer to the "Renesas Technology Corp." Hompage (http:/ /www.renesas.com/en/rom).
As for the Development tools and related documents, refer to the Software and Tools (http://www.renesas.com/ en/tools) of "Renesas Technology Corp." Homepage.
4506 Group
Table of contents
Table of contents
CHAPTER 1 HARDWARE
DESCRIPTION ................................................................................................................................ 1-2 FEATURES ...................................................................................................................................... 1-2 APPLICATION ................................................................................................................................ 1-2 PIN CONFIGURATION .................................................................................................................. 1-2 BLOCK DIAGRAM ......................................................................................................................... 1-3 PERFORMANCE OVERVIEW ....................................................................................................... 1-4 PIN DESCRIPTION ........................................................................................................................ 1-5 MULTIFUNCTION ..................................................................................................................... 1-5 PORT FUNCTION .................................................................................................................... 1-6 DEFINITION OF CLOCK AND CYCLE ................................................................................. 1-6 CONNECTIONS OF UNUSED PINS ..................................................................................... 1-7 PORT BLOCK DIAGRAMS ..................................................................................................... 1-8 FUNCTION BLOCK OPERATIONS ........................................................................................... 1-13 CPU .......................................................................................................................................... 1-13 PROGRAM MEMOY (ROM) .................................................................................................. 1-16 DATA MEMORY (RAM) ......................................................................................................... 1-17 INTERRUPT FUNCTION ....................................................................................................... 1-18 EXTERNAL INTERRUPTS .................................................................................................... 1-22 TIMERS ................................................................................................................................... 1-25 WATCHDOG TIMER .............................................................................................................. 1-30 A/D CONVERTER .................................................................................................................. 1-32 RESET FUNCTION ................................................................................................................ 1-37 RAM BACK-UP MODE .......................................................................................................... 1-40 CLOCK CONTROL ................................................................................................................. 1-45 ROM ORDERING METHOD ....................................................................................................... 1-47 LIST OF PRECAUTIONS ............................................................................................................ 1-48 CONTROL REGISTERS .............................................................................................................. 1-51 INSTRUCTIONS ............................................................................................................................ 1-55 SYMBOL .................................................................................................................................. 1-55 INDEX LIST OF INSTRUCTION FUNCTION ..................................................................... 1-56 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) ....................................................... 1-60 MACHINE INSTRUCTIONS (INDEX BY TYPES) .............................................................. 1-88 INSTRUCTION CODE TABLE ............................................................................................ 1-100 BUILT-IN PROM VERSION ...................................................................................................... 1-102
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
i
4506 Group
Table of contents
CHAPTER 2 APPLICATION
2.1 I/O pins .................................................................................................................................... 2-2 2.1.1 I/O ports .......................................................................................................................... 2-2 2.1.2 Related registers ............................................................................................................ 2-5 2.1.3 Port application examples ............................................................................................. 2-9 2.1.4 Notes on use ................................................................................................................ 2-10 2.2 Interrupts ............................................................................................................................... 2-12 2.2.1 Interrupt functions ........................................................................................................ 2-12 2.2.2 Related registers .......................................................................................................... 2-13 2.2.3 Interrupt application examples .................................................................................... 2-16 2.2.4 Notes on use ................................................................................................................ 2-20 2.3 Timers .................................................................................................................................... 2-21 2.3.1 Timer functions ............................................................................................................. 2-21 2.3.2 Related registers .......................................................................................................... 2-22 2.3.3 Timer application examples ........................................................................................ 2-24 2.3.4 Notes on use ................................................................................................................ 2-31 2.4 A/D converter ....................................................................................................................... 2-33 2.4.1 Related registers .......................................................................................................... 2-34 2.4.2 A/D converter application examples .......................................................................... 2-34 2.4.3 Notes on use ................................................................................................................ 2-36 2.5 Reset ....................................................................................................................................... 2-38 2.5.1 Reset circuit .................................................................................................................. 2-38 2.5.2 Internal state at reset .................................................................................................. 2-39 2.5.3 Notes on use ................................................................................................................ 2-39 2.6 RAM back-up ........................................................................................................................ 2-40 2.6.1 RAM back-up mode ..................................................................................................... 2-40 2.6.2 Related registers .......................................................................................................... 2-42 2.6.3 Notes on use ................................................................................................................ 2-46 2.7 Oscillation circuit ................................................................................................................ 2-47 2.7.1 Oscillation circuit .......................................................................................................... 2-47 2.7.2 Oscillation operation .................................................................................................... 2-49 2.7.3 Notes on use ................................................................................................................ 2-50
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
ii
4506 Group
Table of contents
CHAPTER 3 APPENDIX
3.1 Electrical characteristics ..................................................................................................... 3-2 3.1.1 Absolute maximum ratings ............................................................................................ 3-2 3.1.2 Recommended operating conditions ............................................................................ 3-3 3.1.3 Electrical characteristics ................................................................................................ 3-6 3.1.4 A/D converter recommended operating conditions .................................................... 3-7 3.1.5 Basic timing diagram ..................................................................................................... 3-8 3.2 Typical characteristics ......................................................................................................... 3-9 3.2.1 VDD-IDD characteristics ................................................................................................... 3-9 3.2.2 Frequency characteristics ............................................................................................ 3-13 3.2.3 VOL-IOL characteristics (VDD = 5 V) ............................................................................ 3-15 3.2.4 VOL-IOL characteristics (VDD = 3 V) ............................................................................ 3-17 3.2.5 Input threshold (VIH-VIL) characteristics (Ta = 25 C) ............................................ 3-19 3.2.6 VDD-RPU characteristics (Ports P0-P2, D2/C, D3/K, RESET) .................................. 3-22 3.2.7 Analog input current characteristics pins VAIN-IAIN ......................................................................................... 3-23 3.2.8 Analog input current characteristics pins VAIN-IAIN ................................................... 3-25 3.2.9 A/D converter operation current (VDD-AIDD) characteristics (Ta = 25 C) ............ 3-27 3.2.10 A/D converter typical characteristics ....................................................................... 3-28 3.3 List of precautions .............................................................................................................. 3-31 3.3.1 Program counter ........................................................................................................... 3-31 3.3.2 Stack registers (SKs) ................................................................................................... 3-31 3.3.3 Notes on I/O port ......................................................................................................... 3-31 3.3.4 Notes on interrupt ........................................................................................................ 3-33 3.3.5 Notes on timer .............................................................................................................. 3-35 3.3.6 Notes on A/D conversion ............................................................................................ 3-36 3.3.7 Notes on reset .............................................................................................................. 3-37 3.3.8 Notes on RAM back-up ............................................................................................... 3-38 3.3.9 Notes on oscillation control ........................................................................................ 3-39 3.3.10 Electric Characteristic Differences Between Mask ROM and One Time PROM Version MCU ... 3-39 3.3.11 Notes on Power Source Voltage ............................................................................. 3-39 3.4 Notes on noise ..................................................................................................................... 3-40 3.4.1 Shortest wiring length .................................................................................................. 3-40 3.4.2 Connection of bypass capacitor across VSS line and VDD line ............................... 3-42 3.4.3 wiring to analog input pins ......................................................................................... 3-43 3.4.4 Oscillator concerns ....................................................................................................... 3-43 3.4.5 setup for I/O ports ....................................................................................................... 3-44 3.4.6 providing of watchdog timer function by software ................................................... 3-44 3.5 Package outline ................................................................................................................... 3-46
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
iii
4506 Group
List of figures
List of figures
CHAPTER 1 HARDWARE
Pin configuration (top view) (4506 Group) ............................................................................. 1-2 Block diagram (4506 Group) ...................................................................................................... 1-3 Port block diagram (1) ................................................................................................................ 1-8 Port block diagram (2) ................................................................................................................ 1-9 Port block diagram (3) .............................................................................................................. 1-10 Port block diagram (4) .............................................................................................................. 1-11 External interrupt circuit structure ........................................................................................ 1-12 Fig. 1 AMC instruction execution example ............................................................................... 1-13 Fig. 2 RAR instruction execution example ............................................................................... 1-13 Fig. 3 Registers A, B and register E ........................................................................................ 1-13 Fig. 4 TABP p instruction execution example .......................................................................... 1-13 Fig. 5 Stack registers (SKs) structure ....................................................................................... 1-14 Fig. 6 Example of operation at subroutine call ....................................................................... 1-14 Fig. 7 Program counter (PC) structure ..................................................................................... 1-15 Fig. 8 Data pointer (DP) structure ............................................................................................. 1-15 Fig. 9 SD instruction execution example .................................................................................. 1-15 Fig. 10 ROM map of M34506M4/M34506E4 ............................................................................ 1-16 Fig. 11 Page 1 (addresses 008016 to 00FF16) structure ......................................................... 1-16 Fig. 12 RAM map ......................................................................................................................... 1-17 Fig. 13 Program example of interrupt processing ................................................................... 1-19 Fig. 14 Internal state when interrupt occurs ............................................................................ 1-19 Fig. 15 Interrupt system diagram ............................................................................................... 1-19 Fig. 16 Interrupt sequence .......................................................................................................... 1-21 Fig. 17 External interrupt circuit structure ................................................................................ 1-22 Fig. 18 External 0 interrupt program example-1 ...................................................................... 1-24 Fig. 19 External 0 interrupt program example-2 ...................................................................... 1-24 Fig. 20 External 0 interrupt program example-3 ...................................................................... 1-24 Fig. 21 Auto-reload function ....................................................................................................... 1-25 Fig. 22 Timers structure .............................................................................................................. 1-26 Fig. 23 Count timing diagram at CNTR input .......................................................................... 1-29 Fig. 24 Timer count start timing and count time when operation starts (T1, T2) ............... 1-29 Fig. 25 Watchdog timer function ................................................................................................ 1-30 Fig. 26 Program example to start/stop watchdog timer ......................................................... 1-31 Fig. 27 Program example to enter the RAM back-up mode when using the watchdog timer ........................................................................................................................................................ 1-31 Fig. 28 A/D conversion circuit structure ................................................................................... 1-32 Fig. 29 A/D conversion timing chart .......................................................................................... 1-34 Fig. 30 Setting registers .............................................................................................................. 1-34 Fig. 31 Comparator operation timing chart ............................................................................... 1-35 Fig. 32 Definition of A/D conversion accuracy ........................................................................ 1-36 Fig. 33 Reset release timing ...................................................................................................... 1-37 Fig. 34 RESET pin input waveform and reset operation ....................................................... 1-37 Fig. 35 Structure of reset pin and its peripherals, and power-on reset operation ............. 1-38 Fig. 36 Internal state at reset .................................................................................................... 1-39 Fig. 37 State transition ................................................................................................................ 1-42 Fig. 38 Set source and clear source of the P flag ................................................................. 1-42 Fig. 39 Start condition identified example using the SNZP instruction ................................ 1-42 Fig. 40 Clock control circuit structure ....................................................................................... 1-45
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
iv
4506 Group
List of figures
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig.
41 42 43 44 45 46 47 48 49 50 51 52 53 54
Switch to ceramic resonance/RC oscillation ............................................................... 1-46 Handling of XIN and XOUT when operating on-chip oscillator .................................... 1-46 Ceramic resonator external circuit ............................................................................... 1-46 External RC oscillation circuit ....................................................................................... 1-46 External clock input circuit ............................................................................................ 1-47 Timer count start timing and count time when operation starts (T1, T2) ............... 1-48 External 0 interrupt program example-1 ...................................................................... 1-49 External 0 interrupt program example-2 ...................................................................... 1-49 External 0 interrupt program example-3 ...................................................................... 1-49 A/D conversion interrupt program example ................................................................ 1-50 Analog input external circuit example-1 ...................................................................... 1-50 Analog input external circuit example-2 ...................................................................... 1-50 Flow of writing and test of the product shipped in blank ....................................... 1-102 Pin configuration of built-in PROM version .............................................................. 1-103
CHAPTER 2 APPLICATION
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.1.1 2.1.2 2.2.1 2.2.2 2.2.3 2.2.4 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.3.7 2.3.8 2.3.9 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.5.1 2.5.2 2.5.3 2.6.1 2.7.1 2.7.2 2.7.3 2.7.4 2.7.5 Key input by key scan ................................................................................................. 2-9 Key scan input timing .................................................................................................. 2-9 INT interrupt operation example .............................................................................. 2-16 INT interrupt setting example ................................................................................... 2-17 Timer 1 constant period interrupt setting example ................................................ 2-18 Timer 2 constant period interrupt setting example ................................................ 2-19 Peripheral circuit example ......................................................................................... 2-24 Watchdog timer function ............................................................................................ 2-25 Constant period measurement setting example ..................................................... 2-26 CNTR output setting example .................................................................................. 2-27 CNTR input setting example ..................................................................................... 2-28 Timer start by external input setting example (1) ................................................. 2-29 Timer start by external input setting example (2) ................................................. 2-30 Watchdog timer setting example .............................................................................. 2-31 Timer count start timing and count time when operation starts (T1, T2) ................ 2-32 A/D converter structure ............................................................................................. 2-33 A/D conversion mode setting example .................................................................... 2-35 Analog input external circuit example-1 .................................................................. 2-36 Analog input external circuit example-2 .................................................................. 2-36 A/D converter operating mode program example .................................................. 2-36 Structure of reset pin and its peripherals, and power-on reset operation ......... 2-38 Oscillation stabilizing time after system is released from reset .......................... 2-38 Internal state at reset ................................................................................................ 2-39 Start condition identified example ............................................................................ 2-41 Switch to ceramic resonance/RC oscillation .......................................................... 2-47 Handling of XIN and XOUT when operating on-chip oscillator ................................ 2-47 Ceramic resonator external circuit ........................................................................... 2-48 External RC oscillation circuit .................................................................................. 2-48 Structure of clock control circuit .............................................................................. 2-49
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
v
4506 Group
List of figures
CHAPTER 3 APPENDIX
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 3.2.1 A/D conversion characteristics data ........................................................................ 3-28 3.3.1 External 0 interrupt program example-1 ................................................................. 3-33 3.3.2 External 0 interrupt program example-2 ................................................................. 3-34 3.3.3 External 0 interrupt program example-3 ................................................................. 3-34 3.3.4 Timer count start timing and count time when operation starts (T1, T2) ................ 3-35 3.3.5 Analog input external circuit example-1 .................................................................. 3-36 3.3.6 Analog input external circuit example-2 .................................................................. 3-36 3.3.7 A/D converter operating mode program example .................................................. 3-36 3.4.1 Selection of packages ............................................................................................... 3-40 3.4.2 Wiring for the RESET input pin ............................................................................... 3-40 3.4.3 Wiring for clock I/O pins ........................................................................................... 3-41 3.4.4 Wiring for CNVSS pin .................................................................................................. 3-41 3.4.5 Wiring for the VPP pin of the built-in PROM version ............................................. 3-42 3.4.6 Bypass capacitor across the VSS line and the VDD line ........................................ 3-42 3.4.7 Analog signal line and a resistor and a capacitor ................................................ 3-43 3.4.8 Wiring for a large current signal line ...................................................................... 3-43 3.4.9 Wiring to a signal line where potential levels change frequently ....................... 3-44 3.4.10 VSS pattern on the underside of an oscillator ...................................................... 3-44 3.4.11 Watchdog timer by software ................................................................................... 3-45
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
vi
4506 Group
List of tables
List of tables
CHAPTER 1 HARDWARE
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Selection of system clock .............................................................................................. 1-6 1 ROM size and pages .................................................................................................... 1-16 2 RAM size ........................................................................................................................ 1-17 3 Interrupt sources ............................................................................................................ 1-18 4 Interrupt request flag, interrupt enable bit and skip instruction .............................. 1-18 5 Interrupt enable bit function ......................................................................................... 1-18 6 Interrupt control registers ............................................................................................. 1-20 7 External interrupt activated conditions ........................................................................ 1-22 8 External interrupt control register ................................................................................ 1-23 9 Function related timers ................................................................................................. 1-25 10 Timer control registers ................................................................................................ 1-27 11 A/D converter characteristics ..................................................................................... 1-32 12 A/D control registers ................................................................................................... 1-33 13 Change of successive comparison register AD during A/D conversion .............. 1-34 14 Port state at reset ....................................................................................................... 1-38 15 Functions and states retained at RAM back-up ..................................................... 1-40 16 Return source and return condition .......................................................................... 1-41 17 Key-on wakeup control register ................................................................................. 1-43 18 Pull-up control register and interrupt control register ............................................ 1-44 19 Clock control register MR .......................................................................................... 1-47 20 Product of built-in PROM version ........................................................................... 1-102
CHAPTER 2 APPLICATION
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.1.6 2.1.7 2.1.8 2.2.1 2.2.2 2.2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.4.1 2.4.2 2.6.1 2.6.2 2.6.3 2.6.4 2.6.5 2.6.6 Key-on wakeup control register K0 ........................................................................ 2-5 Pull-up control register PU0 .................................................................................... 2-5 Key-on wakeup control register K1 ........................................................................ 2-6 Pull-up control register PU1 .................................................................................... 2-6 Key-on wakeup control register K2 ........................................................................ 2-7 Pull-up control register PU2 .................................................................................... 2-7 Timer control register W6 ........................................................................................ 2-8 Connections of unused pins .................................................................................. 2-11 Interrupt control register V1 ................................................................................... 2-13 Interrupt control register V2 ................................................................................... 2-14 Interrupt control register I1 .................................................................................... 2-15 Interrupt control register V1 ................................................................................... 2-22 Timer control register W1 ...................................................................................... 2-22 Timer control register W2 ...................................................................................... 2-23 Timer control register W6 ...................................................................................... 2-23 Recommended operating condition of pulse width input to CNTR pin ........... 2-32 A/D control register Q1 .......................................................................................... 2-34 Recommended operating conditions (when using A/D converter) ................... 2-37 Functions and states retained at RAM back-up mode ...................................... 2-40 Return source and return condition ...................................................................... 2-41 Start condition identification ................................................................................... 2-41 Key-on wakeup control register K0 ...................................................................... 2-42 Key-on wakeup control register K1 ...................................................................... 2-42 Key-on wakeup control register K2 ...................................................................... 2-43
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
vii
4506 Group
List of tables
Table Table Table Table Table
2.6.7 Pull-up control register PU0 .................................................................................. 2-43 2.6.8 Pull-up control register PU1 .................................................................................. 2-44 2.6.9 Pull-up control register PU2 .................................................................................. 2-44 2.6.10 Interrupt control register I1 .................................................................................. 2-45 2.7.1 Maximum value of oscillation frequency and supply voltage ............................ 2-48
CHAPTER 3 APPENDIX
Table Table Table Table Table Table Table Table Table 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6 3.3.1 3.3.2 3.3.3 Absolute maximum ratings ....................................................................................... 3-2 Recommended operating conditions 1 ................................................................... 3-3 Recommended operating conditions 2 ................................................................... 3-5 Electrical characteristics ........................................................................................... 3-6 A/D converter recommended operating conditions ............................................... 3-7 A/D converter characteristcs .................................................................................... 3-7 Connections of unused pins .................................................................................. 3-32 Recommended operating condition of pulse width input to CNTR pin ........... 3-35 Recommended operating conditions (when using A/D converter) ................... 3-37
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
viii
CHAPTER 1 HARDWARE
DESCRIPTION FEATURES APPLICATION PIN CONFIGURATION BLOCK DIAGRAM PERFORMANCE OVERVIEW PIN DESCRIPTION FUNCTION BLOCK OPERATIONS ROM ORDERING METHOD LIST OF PRECAUTIONS CONTROL REGISTERS INSTRUCTIONS BUILT-IN PROM VERSION
HARDWARE 4506 Group DESCRIPTION/FEATURES/APPLICATION/PIN CONFIGURATION
DESCRIPTION
The 4506 Group is a 4-bit single-chip microcomputer designed with CMOS technology. Its CPU is that of the 4500 series using a simple, high-speed instruction set. The computer is equipped with two 8-bit timers (each timer has a reload register), interrupts, and 10-bit A/D converter. The various microcomputers in the 4506 Group include variations of the built-in memory size as shown in the table below.
FEATURES
qMinimum instruction execution time ................................ 0.68 s (at 4.4 MHz oscillation frequency, in high-speed mode) qSupply voltage .......................................................... 2.0 V to 5.5 V (It depends on the oscillation frequency and operating mode.)
q Timers Timer 1 ...................................... 8-bit timer with a reload register Timer 2 ...................................... 8-bit timer with a reload register q Interrupt ........................................................................ 4 sources q Key-on wakeup function pins ................................................... 12 q Input/Output port ...................................................................... 14 q A/D converter .................. 10-bit successive comparison method q Watchdog timer q Clock generating circuit (ceramic resonator/RC oscillation) q LED drive directly enabled (port D)
APPLICATION
Electrical household appliance, consumer electronic products, office automation equipment, etc.
Part number M34506M2-XXXFP M34506M4-XXXFP M34506E4FP (Note) Note: Shipped in blank.
ROM (PROM) size ( 10 bits) 2048 words 4096 words 4096 words
RAM size ( 4 bits) 128 words 256 words 256 words
Package PRSP0020DA-A PRSP0020DA-A PRSP0020DA-A
ROM type Mask ROM Mask ROM One Time PROM
PIN CONFIGURATION
VDD VSS XIN XOUT CNVSS RESET P21/AIN1 P20/AIN0 D3/K D2/C
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
P00 P01 P02 P03 P10 P11 P12/CNTR P13/INT D0 D1
Outline PRSP0020DA-A (20P2N-A)
Pin configuration (top view) (4506 Group)
M34506Mx-XXXFP M34506E4FP
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-2
4506 Group
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
BLOCK DIAGRAM
4 4 2 4
Block diagram (4506 Group)
I/O port
Port P1 Port P2 Port D
Port P0
Internal peripheral functions
System clock generating circuit XIN -XOUT
Timer
Timer 1 (8 bits)
Timer 2 (8 bits)
Watchdog timer (16 bits)
Memory
ROM
2048, 4096 words 10 bits
A/D converter (10 bits 2 ch)
4500 Series CPU core
ALU (4 bits)
Register A (4 bits) Register B (4 bits) Register E (8 bits) Register D (3 bits) Stack register SK (8 levels) Interrupt stack register SDP (1level)
RAM
128, 256 words 4 bits
BLOCK DIAGRAM
HARDWARE
1-3
HARDWARE 4506 Group PERFORMANCE OVERVIEW
PERFORMANCE OVERVIEW
Parameter Number of basic instructions Minimum instruction execution time Memory sizes ROM M34506M2 M34506M4/E4 RAM M34506M2 M34506M4/E4 Input/Output D0-D3 I/O ports Function 110 0.68 s (at 4.4 MHz oscillation frequency, in high-speed mode) 2048 words 10 bits 4096 words 10 bits 128 words 4 bits 256 words 4 bits Four independent I/O ports . Input is examined by skip decision. Ports D2 and D3 are equipped with a pull-up function and a key-on wakeup function. Both functions can be switched by software. Ports D2 and D3 are also used as ports C and K, respectively. 4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both functions can be switched by software. 4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both functions can be switched by software. Ports P12 and P13 are also used as CNTR and INT, respectively. 2-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both functions can be switched by software. Ports P20 and P21 are also used as AIN0 and AIN1, respectively. 1-bit I/O; Port C is also used as port D2. 1-bit I/O; Port K is also used as port D3. 1-bit I/O; CNTR pin is also used as port P12. 1-bit input; INT pin is also used as port P13. Two independent I/O ports; AIN0, AIN1 are also used as P20 and P21, respectively. 8-bit programmable timer with a reload register. 8-bit programmable timer with a reload register and has a event counter. 10-bit wide, This is equipped with an 8-bit comparator function. 2 channel (AIN0 pin, AIN1 pin) 4 (one for external, two for timer, one for A/D) 1 level 8 levels CMOS silicon gate 20-pin plastic molded SOP (PRSP0020DA-A) -20 C to 85 C 2.0 V to 5.5 V (It depends on the oscillation frequency and operating mode. Refer to the recommended operating condition.) 1.7 mA (Ta=25C, VDD = 5.0 V, 4.0 MHz oscillation frequency, in high-speed mode, output transistors in the cut-off state) 0.5 mA (Ta=25C, VDD = 3.0 V, 2.0 MHz oscillation frequency, in high-speed mode, output transistors in the cut-off state) 0.1 A (Ta=25C, VDD = 5 V, output transistors in the cut-off state)
P00-P03 I/O P10-P13 I/O
P20, P21 I/O
Timers A/D converter
C K CNTR INT AIN0, AIN1 Timer 1 Timer 2
I/O I/O Timer I/O Interrupt input Analog input
Analog input Sources Nesting Subroutine nesting Device structure Package Operating temperature range Supply voltage Interrupt Power Active mode dissipation (typical value) RAM back-up mode
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-4
HARDWARE 4506 Group PIN DESCRIPTION
PIN DESCRIPTION
Pin VDD VSS CNVSS RESET XIN XOUT D0-D3 Name Power supply Ground CNVSS Reset input/output System clock input System clock output I/O port D Input/Output -- -- -- I/O Input Output I/O Function Connected to a plus power supply. Connected to a 0 V power supply. Connect CNVSS to VSS and apply "L" (0V) to CNVSS certainly. An N-channel open-drain I/O pin for a system reset. When the watchdog timer or the built-in power-on reset causes the system to be reset, the RESET pin outputs "L" level. I/O pins of the system clock generating circuit. When using a ceramic resonator, connect it between pins XIN and XOUT. A feedback resistor is built-in between them. When using the RC oscillation, connect a resistor and a capacitor to XIN, and leave XOUT pin open. Each pin of port D has an independent 1-bit wide I/O function. Each pin has an output latch. For input use, set the latch of the specified bit to "1." Input is examined by skip decision. The output structure is N-channel open-drain. Ports D2 and D3 are equipped with a pull-up function and a key-on wakeup function. Both functions can be switched by software. Ports D2 and D3 are also used as ports C and K, respectively. Port P0 serves as a 4-bit I/O port, and it can be used as inputs when the output latch is set to "1." The output structure is N-channel open-drain. Port P0 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Port P1 serves as a 4-bit I/O port, and it can be used as inputs when the output latch is set to "1." The output structure is N-channel open-drain. Port P1 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Ports P12 and P13 are also used as CNTR and INT, respectively. Port P2 serves as a 2-bit I/O port, and it can be used as inputs when the output latch is set to "1." The output structure is N-channel open-drain. Port P2 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Ports P20 and P21 are also used as AIN0 and AIN1, respectively. 1-bit I/O port. Port C can be used as inputs when the output latch is set to "1." The output structure is N-channel open-drain. Port C has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Port C is also used as port D2. 1-bit I/O port. Port K can be used as inputs when the output latch is set to "1." The output structure is N-channel open-drain. Port K has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Port K is also used as port D3. CNTR pin has the function to input the clock for the timer 2 event counter, and to output the timer 1 or timer 2 underflow signal divided by 2. This pin is also used as port P12. INT pin accepts external interrupts. It has the key-on wakeup function which can be switched by software. This pin is also used as port P13. A/D converter analog input pins. AIN0 and AIN1 are also used as ports P20 and P21, respectively.
P00-P03
I/O port P0
I/O
P10-P13
I/O port P1
I/O
P20, P21
I/O port P2
I/O
Port C
I/O port C
I/O
Port K
I/O port K
I/O
CNTR
Timer input/output
I/O
INT AIN0-AIN1
Interrupt input Analog input
Input Input
MULTIFUNCTION
Pin D2 D3 P12 P13 Multifunction C K CNTR INT Pin C K CNTR INT Multifunction D2 D3 P12 P13 Pin P20 P21 Multifunction AIN0 AIN1 Pin AIN0 AIN1 Multifunction P20 P21
Notes 1: Pins except above have just single function. 2: The input/output of D2, D3, P12 and P13 can be used even when C, K, CNTR (input) and INT are selected. 3: The input of P12 can be used even when CNTR (output) is selected. 4: The input/output of P20, P21 can be used even when AIN0, AIN1 are selected.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-5
HARDWARE 4506 Group PIN DESCRIPTION
DEFINITION OF CLOCK AND CYCLE
q Operation source clock The operation source clock is the source clock to operate this product. In this product, the following clocks are used. * External ceramic resonator * External RC oscillation * Clock (f(XIN)) by the external clock * Clock (f(RING)) of the on-chip oscillator which is the internal oscillator. q System clock The system clock is the basic clock for controlling this product. The system clock is selected by the bits 2 and 3 of the clock control register MR. Table Selection of system clock Register MR System clock MR3 MR2 (Note 1) 0 0 f(XIN) or f(RING) 0 1 f(XIN)/2 or f(RING)/2 1 0 f(XIN)/4 or f(RING)/4 1 1 f(XIN)/8 or f(RING)/8 q Instruction clock The instruction clock is a signal derived by dividing the system clock by 3. The one instruction clock cycle generates the one machine cycle. q Machine cycle The machine cycle is the standard cycle required to execute the instruction.
Operation mode High-speed mode Middle-speed mode Low-speed mode Default mode
Notes 1: The on-chip oscillator clock is f(RING), the clock by the ceramic resonator, RC oscillation or external clock is f(XIN). 2: The default mode is selected after system is released from reset and is returned from RAM back-up.
PORT FUNCTION
Port Port D D0, D1 D2/C D3/K Pin Input Output I/O (4) Output structure N-channel open-drain I/O unit 1 Control instructions SD, RD SZD, CLD SCP, RCP SNZCP IAK, OKA OP0A IAP0 Control registers PU2, K2 Remark Built-in programmable pull-up functions Key-on wakeup functions (programmable) Built-in programmable pull-up functions Key-on wakeup functions (programmable) Built-in programmable pull-up functions Key-on wakeup functions (programmable) Built-in programmable pull-up functions Key-on wakeup functions (programmable)
Port P0 P00-P03
I/O (4)
N-channel open-drain
4
PU0, K0
Port P1 P10, P11 P12/CNTR, P13/INT Port P2 P20/AIN0 P21/AIN1
I/O (4)
N-channel open-drain
4
OP1A IAP1
PU1, K1 W6, I1
I/O (2)
N-channel open-drain
2
OP2A IAP2
PU2, K2 Q1
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-6
HARDWARE 4506 Group PIN DESCRIPTION
CONNECTIONS OF UNUSED PINS
Pin XIN XOUT Connection Connect to VSS. Open. Usage condition System operates by the on-chip oscillator. (Note 1) System operates by the external clock. (The ceramic resonator is selected with the CMCK instruction.) System operates by the RC oscillator. (The RC oscillation is selected with the CRCK instruction.) System operates by the on-chip oscillator. (Note 1)
D0, D1
D2/C D3/K P00-P03
P10, P11 P12/CNTR P13/INT
Open. (Output latch is set to "1.") Open. (Output latch is set to "0.") Connect to VSS. Open. (Output latch is set to "1.") Open. (Output latch is set to "0.") Connect to VSS. Open. (Output latch is set to "1.") Open. (Output latch is set to "0.") Connect to VSS. Open. (Output latch is set to "1.") Open. (Output latch is set to "0.") Connect to VSS. Open. (Output latch is set to "1.") Open. (Output latch is set to "0.") Connect to VSS. Open. (Output latch is set to "1.") Open. (Output latch is set to "0.") Connect to VSS.
P20/AIN0 P21/AIN1
The key-on wakeup function is not selected. (Note 4) The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3) The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3) The key-on wakeup function is not selected. (Note 4) The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3) The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3) The key-on wakeup function is not selected. (Note 4) The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3) The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3) The key-on wakeup function is not selected. The input to INT pin is disabled. (Notes 4, 5) The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3) The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3) The key-on wakeup function is not selected. (Note 4) The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3) The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3)
Notes 1: When the ceramic resonator or the RC oscillation is not selected by program, system operates by the on-chip oscillator (internal oscillator). 2: When the pull-up function is left valid, the supply current is increased. Do not select the pull-up function. 3: When the key-on wakeup function is left valid, the system returns from the RAM back-up state immediately after going into the RAM back-up state. Do not select the key-on wakeup function. 4: When selecting the key-on wakeup function, select also the pull-up function. 5: Clear the bit 3 (I13) of register I1 to "0" to disable to input to INT pin (after reset: I13 = "0") (Note when connecting to VSS) q Connect the unused pins to VSS using the thickest wire at the shortest distance against noise.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-7
HARDWARE 4506 Group PIN DESCRIPTION
PORT BLOCK DIAGRAMS
Skip decision (SZD instruction) (Note 1) CLD instruction SD instruction RD instruction S RQ D0, D1
Register Y
Decoder
Pull-up transistor
Register Y
Decoder K22 Key-on wakeup "L" level detection circuit Skip decision (SZD instruction) S
Skip decision (SNZCP instruction)
PU22
CLD instruction SD instruction RD instruction SCP instruction RCP instruction
(Note 1) D2/C (Note 2)
RQ S RQ
Pull-up transistor
Register Y
Decoder K23 Key-on wakeup "L" level detection circuit Skip decision (SZD instruction) CLD instruction S IAK instruction Register A
PU23
(Note 1) D3/K (Note 2)
SD instruction RD instruction A0 OKA instruction RQ D TQ
Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to ports D2/C and D3/K must be VDD or less.
Port block diagram (1)
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-8
HARDWARE 4506 Group PIN DESCRIPTION
Pull-up transistor
PU0i (Note 2) Register A IAP0 instruction Ai (Note 2) Ai OP0A instruction D T Q K0i (Note 1) P00, P01 (Note 4)
Key-on wakeup input
"L" level detection circuit
Pull-up transistor
PU0j Register A IAP0 instruction Aj (Note 3) Aj OP0A instruction D T Q K0j Key-on wakeup "L" level detection circuit
(Note 3)
(Note 1) P02, P03 (Note 4)
Notes 1: This symbol represents a parasitic diode on the port. 2: i represents 0 or 1. 3: j represents 2 or 3. 4: Applied potential to port P0 must be VDD or less.
Port block diagram (2)
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-9
HARDWARE 4506 Group PIN DESCRIPTION
Pull-up transistor
K1i (Note 2) PU1i (Note 2)
Key-on wakeup input
"L" level detection circuit IAP1 instruction
Register A Ai (Note 2) Ai OP1A instruction D T Q
(Note 1) P10, P11 (Note 3)
Pull-up transistor
K12 PU12
Key-on wakeup input
"L" level detection circuit W21 W20
Clock input for timer 2 event counter IAP1 instruction Register A A2 A2 OP1A instruction (Note 1) P12/CNTR (Note 3) D W60 T Q
0 1
Timer 1 or timer 2 underflow signal divided by 2
K13 "L" level detection circuit K13
Pull-up transistor
PU13
Key-on wakeup input
External 0 interrupt
External interrupt circuit
IAP1 instruction (Note 1) P13/INT (Note 3)
Register A A3 A3
D T Q
OP1A instruction
Notes 1: This symbol represents a parasitic diode on the port. 2: i represents 0 or 1. 3: Applied potential to port P1 must be VDD or less.
Port block diagram (3)
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-10
HARDWARE 4506 Group PIN DESCRIPTION
K20
Pull-up transistor
PU20
Key-on wakeup input
"L" level detection circuit
Register A A0 A0
IAP2 instruction (Note 1) P20/AIN0 (Note 3) Q Q1 Decoder
D T
OP2A instruction
Analog input
K21
Pull-up transistor
PU21
Key-on wakeup input
Register A A1 A1 OP2A instruction
"L" level detection circuit
IAP2 instruction (Note 1) P21/AIN1 (Note 3) D T Q Q1 Decoder
Analog input
Notes 1: This symbol represents a parasitic diode on the port. 2: i represents 0 or 1. 3: Applied potential to port P2 must be VDD or less.
Port block diagram (4)
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-11
HARDWARE 4506 Group PIN DESCRIPTION
(Note) P13/INT I13
I12 Falling
0 1
One-sided edge detection circuit
I11
0
EXF0
1 Both edges detection circuit
External 0 interrupt
Rising K13
Wakeup Skip
Timer 1 count start synchronization circuit input
SNZI0 instruction
*
This symbol represents a parasitic diode on the port.
External interrupt circuit structure
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-12
HARDWARE 4506 Group FUNCTION BLOCK OPERATIONS
FUNCTION BLOCK OPERATIONS CPU (1) Arithmetic logic unit (ALU)
The arithmetic logic unit ALU performs 4-bit arithmetic such as 4bit data addition, comparison, AND operation, OR operation, and bit manipulation.
(CY) (M(DP)) Addition (A)
Fig. 1 AMC instruction execution example
ALU
(2) Register A and carry flag
Register A is a 4-bit register used for arithmetic, transfer, exchange, and I/O operation. Carry flag CY is a 1-bit flag that is set to "1" when there is a carry with the AMC instruction (Figure 1). It is unchanged with both A n instruction and AM instruction. The value of A0 is stored in carry flag CY with the RAR instruction (Figure 2). Carry flag CY can be set to "1" with the SC instruction and cleared to "0" with the RC instruction.
SC instruction
RC instruction
CY
A3 A2 A1 A0 RAR instruction
(3) Registers B and E
Register B is a 4-bit register used for temporary storage of 4-bit data, and for 8-bit data transfer together with register A. Register E is an 8-bit register. It can be used for 8-bit data transfer with register B used as the high-order 4 bits and register A as the low-order 4 bits (Figure 3). Register E is undefined after system is released from reset and returned from the RAM back-up. Accordingly, set the initial value.
A0
CY A3 A2 A1
Fig. 2 RAR instruction execution example
Register B
TAB instruction
Register A
B3 B2 B1 B0
A3 A2 A1 A0
(4) Register D
Register D is a 3-bit register. It is used to store a 7-bit ROM address together with register A and is used as a pointer within the specified page when the TABP p, BLA p, or BMLA p instruction is executed (Figure 4). Register D is undefined after system is released from reset and returned from the RAM back-up. Accordingly, set the initial value.
TEAB instruction Register E E7 E6 E5 E4 E3 E2 E1 E0 TABE instruction B3 B2 B1 B0 Register B A3 A2 A1 A0 Register A
TBA instruction
Fig. 3 Registers A, B and register E
TABP p instruction Specifying address
ROM 8 4 0
PCH p6 p5 p4 p3 p2 p1 p0
PCL DR2DR1DR0 A3 A2 A1 A0
Low-order 4bits Register A (4) Middle-order 4 bits Register B (4)
Immediate field value p
The contents of The contents of register D register A
Fig. 4 TABP p instruction execution example
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-13
HARDWARE 4506 Group FUNCTION BLOCK OPERATIONS
(5) Stack registers (SKS) and stack pointer (SP)
Stack registers (SKs) are used to temporarily store the contents of program counter (PC) just before branching until returning to the original routine when; * branching to an interrupt service routine (referred to as an interrupt service routine), * performing a subroutine call, or * executing the table reference instruction (TABP p). Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these operations together. The contents of registers SKs are destroyed when 8 levels are exceeded. The register SK nesting level is pointed automatically by 3-bit stack pointer (SP). The contents of the stack pointer (SP) can be transferred to register A with the TASP instruction. Figure 5 shows the stack registers (SKs) structure. Figure 6 shows the example of operation at subroutine call.
Program counter (PC) Executing BM instruction SK0 SK1 SK2 SK3 SK4 SK5 SK6 SK7 Executing RT instruction (SP) = 0 (SP) = 1 (SP) = 2 (SP) = 3 (SP) = 4 (SP) = 5 (SP) = 6 (SP) = 7
Stack pointer (SP) points "7" at reset or returning from RAM back-up mode. It points "0" by executing the first BM instruction, and the contents of program counter is stored in SK0. When the BM instruction is executed after eight stack registers are used ((SP) = 7), (SP) = 0 and the contents of SK0 is destroyed.
Fig. 5 Stack registers (SKs) structure
(6) Interrupt stack register (SDP)
Interrupt stack register (SDP) is a 1-stage register. When an interrupt occurs, this register (SDP) is used to temporarily store the contents of data pointer, carry flag, skip flag, register A, and register B just before an interrupt until returning to the original routine. Unlike the stack registers (SKs), this register (SDP) is not used when executing the subroutine call instruction and the table reference instruction.
(SP) 0 (SK0) 000116 (PC) SUB1
Main program Address 000016 NOP 000116 BM SUB1 000216 NOP
Subroutine
SUB1 : NOP * * * RT
(7) Skip flag
Skip flag controls skip decision for the conditional skip instructions and continuous described skip instructions. When an interrupt occurs, the contents of skip flag is stored automatically in the interrupt stack register (SDP) and the skip condition is retained.
(PC) (SK0) (SP) 7
Note : Returning to the BM instruction execution address with the RT instruction, and the BM instruction becomes the NOP instruction.
Fig. 6 Example of operation at subroutine call
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-14
HARDWARE 4506 Group FUNCTION BLOCK OPERATIONS
(8) Program counter (PC)
Program counter (PC) is used to specify a ROM address (page and address). It determines a sequence in which instructions stored in ROM are read. It is a binary counter that increments the number of instruction bytes each time an instruction is executed. However, the value changes to a specified address when branch instructions, subroutine call instructions, return instructions, or the table reference instruction (TABP p) is executed. Program counter consists of PCH (most significant bit to bit 7) which specifies to a ROM page and PCL (bits 6 to 0) which specifies an address within a page. After it reaches the last address (address 127) of a page, it specifies address 0 of the next page (Figure 7). Make sure that the PCH does not specify after the last page of the built-in ROM.
Program counter p6 p5 p4 p3 p2 p1 p0 a6 a5 a4 a3 a2 a1 a0
PCH Specifying page
PCL Specifying address
Fig. 7 Program counter (PC) structure
Data pointer (DP) Z1 Z0 X3 X2 X1 X0 Y3 Y2 Y1 Y0
(9) Data pointer (DP)
Data pointer (DP) is used to specify a RAM address and consists of registers Z, X, and Y. Register Z specifies a RAM file group, register X specifies a file, and register Y specifies a RAM digit (Figure 8). Register Y is also used to specify the port D bit position. When using port D, set the port D bit position to register Y certainly and execute the SD, RD, or SZD instruction (Figure 9). * Note Register Z of data pointer is undefined after system is released from reset. Also, registers Z, X and Y are undefined in the RAM back-up. After system is returned from the RAM back-up, set these registers.
Register Y (4)
Specifying RAM digit
Register X (4)
Specifying RAM file
Register Z (2)
Specifying RAM file group
Fig. 8 Data pointer (DP) structure
Specifying bit position Set
D3 D2 D1 D0
0
0
0
1
1 Port D output latch
Register Y (4)
Fig. 9 SD instruction execution example
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-15
HARDWARE 4506 Group FUNCTION BLOCK OPERATIONS
PROGRAM MEMOY (ROM)
The program memory is a mask ROM. 1 word of ROM is composed of 10 bits. ROM is separated every 128 words by the unit of page (addresses 0 to 127). Table 1 shows the ROM size and pages. Figure 10 shows the ROM map of M34506M4. Table 1 ROM size and pages Part number M34506M2 M34506M4 M34506E4 ROM (PROM) size ( 10 bits) 2048 words 4096 words 4096 words Pages 16 (0 to 15) 32 (0 to 31) 32 (0 to 31)
98 000016 007F16 008016 00FF16 010016 017F16 018016
7
6
5
4
3
2
10 Page 0
Interrupt address page Subroutine special page
Page 1 Page 2 Page 3
A part of page 1 (addresses 008016 to 00FF16) is reserved for interrupt addresses (Figure 11). When an interrupt occurs, the address (interrupt address) corresponding to each interrupt is set in the program counter, and the instruction at the interrupt address is executed. When using an interrupt service routine, write the instruction generating the branch to that routine at an interrupt address. Page 2 (addresses 010016 to 017F16) is the special page for subroutine calls. Subroutines written in this page can be called from any page with the 1-word instruction (BM). Subroutines extending from page 2 to another page can also be called with the BM instruction when it starts on page 2. ROM pattern (bits 7 to 0) of all addresses can be used as data areas with the TABP p instruction.
0FFF16
Page 31
Fig. 10 ROM map of M34506M4/M34506E4
008016 008216 008416 008616 008816 008A16 008C16 008E16
98 765 432 10 External 0 interrupt address
Timer 1 interrupt address Timer 2 interrupt address
A/D interrupt address
00FF16
Fig. 11 Page 1 (addresses 008016 to 00FF16) structure
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-16
HARDWARE 4506 Group FUNCTION BLOCK OPERATIONS
DATA MEMORY (RAM)
1 word of RAM is composed of 4 bits, but 1-bit manipulation (with the SB j, RB j, and SZB j instructions) is enabled for the entire memory area. A RAM address is specified by a data pointer. The data pointer consists of registers Z, X, and Y. Set a value to the data pointer certainly when executing an instruction to access RAM. Table 2 shows the RAM size. Figure 12 shows the RAM map. * Note Register Z of data pointer is undefined after system is released from reset. Also, registers Z, X and Y are undefined in the RAM back-up. After system is returned from the RAM back-up, set these registers.
Table 2 RAM size Part number M34506M2 M34506M4 M34506E4 RAM size 128 words 4 bits (512 bits) 256 words 4 bits (1024 bits) 256 words 4 bits (1024 bits)
RAM 256 words 4 bits (1024 bits)
Register Z Register X
0
1
2
0 ... 6 7 3
........ 15
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 256 words (1024 bits) M34506M4/E4 128 words (512 bits) M34506M2
Z=0, X=0 to 15 Z=0, X=0 to 7
Fig. 12 RAM map
Register Y
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-17
HARDWARE 4506 Group FUNCTION BLOCK OPERATIONS
INTERRUPT FUNCTION
The interrupt type is a vectored interrupt branching to an individual address (interrupt address) according to each interrupt source. An interrupt occurs when the following 3 conditions are satisfied. * An interrupt activated condition is satisfied (request flag = "1") * Interrupt enable bit is enabled ("1") * Interrupt enable flag is enabled (INTE = "1") Table 3 shows interrupt sources. (Refer to each interrupt request flag for details of activated conditions.)
Table 3 Interrupt sources Priority Interrupt name level 1 External 0 interrupt 2 3 4 Timer 1 interrupt Timer 2 interrupt A/D interrupt
Activated condition Level change of INT pin Timer 1 underflow Timer 2 underflow Completion of A/D conversion
Interrupt address Address 0 in page 1 Address 4 in page 1 Address 6 in page 1 Address C in page 1
(1) Interrupt enable flag (INTE)
The interrupt enable flag (INTE) controls whether the every interrupt enable/disable. Interrupts are enabled when INTE flag is set to "1" with the EI instruction and disabled when INTE flag is cleared to "0" with the DI instruction. When any interrupt occurs, the INTE flag is automatically cleared to "0," so that other interrupts are disabled until the EI instruction is executed. Table 4 Interrupt request flag, interrupt enable bit and skip instruction Interrupt name External 0 interrupt Timer 1 interrupt Timer 2 interrupt A/D interrupt Interrupt request flag EXF0 T1F T2F ADF Skip instruction SNZ0 SNZT1 SNZT2 SNZAD Interrupt enable bit V10 V12 V13 V22
(2) Interrupt enable bit
Use an interrupt enable bit of interrupt control registers V1 and V2 to select the corresponding interrupt or skip instruction. Table 4 shows the interrupt request flag, interrupt enable bit and skip instruction. Table 5 shows the interrupt enable bit function.
Table 5 Interrupt enable bit function Interrupt enable bit Occurrence of interrupt Enabled 1 Disabled 0
Skip instruction Invalid Valid
(3) Interrupt request flag
When the activated condition for each interrupt is satisfied, the corresponding interrupt request flag is set to "1." Each interrupt request flag is cleared to "0" when either; * an interrupt occurs, or * the next instruction is skipped with a skip instruction. Each interrupt request flag is set when the activated condition is satisfied even if the interrupt is disabled by the INTE flag or its interrupt enable bit. Once set, the interrupt request flag retains set until a clear condition is satisfied. Accordingly, an interrupt occurs when the interrupt disable state is released while the interrupt request flag is set. If more than one interrupt request flag is set when the interrupt disable state is released, the interrupt priority level is as follows shown in Table 3.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-18
HARDWARE 4506 Group FUNCTION BLOCK OPERATIONS
(4) Internal state during an interrupt
The internal state of the microcomputer during an interrupt is as follows (Figure 14). * Program counter (PC) An interrupt address is set in program counter. The address to be executed when returning to the main routine is automatically stored in the stack register (SK). * Interrupt enable flag (INTE) INTE flag is cleared to "0" so that interrupts are disabled. * Interrupt request flag Only the request flag for the current interrupt source is cleared to "0." * Data pointer, carry flag, skip flag, registers A and B The contents of these registers and flags are stored automatically in the interrupt stack register (SDP).
* Program counter (PC) ............................................................... Each interrupt address * Stack register (SK) The address of main routine to be .................................................................................................... executed when returning * Interrupt enable flag (INTE) .................................................................. 0 (Interrupt disabled) * Interrupt request flag (only the flag for the current interrupt source) ................................................................................... 0 * Data pointer, carry flag, registers A and B, skip flag ........ Stored in the interrupt stack register (SDP) automatically Fig. 14 Internal state when interrupt occurs
(5) Interrupt processing
When an interrupt occurs, a program at an interrupt address is executed after branching a data store sequence to stack register. Write the branch instruction to an interrupt service routine at an interrupt address. Use the RTI instruction to return from an interrupt service routine. Interrupt enabled by executing the EI instruction is performed after executing 1 instruction (just after the next instruction is executed). Accordingly, when the EI instruction is executed just before the RTI instruction, interrupts are enabled after returning the main routine. (Refer to Figure 13)
INT pin (LH or HL input)
EXF0
V10
Address 0 in page 1
Timer 1 underflow
T1F
V12
Address 4 in page 1
Timer 2 underflow
T2F
V13
Address 6 in page 1
Main routine Interrupt service routine
Interrupt occurs
Completion of A/D conversion Activated condition
A DF Request flag (state retained)
V22 Enable bit
INTE
Address C in page 1
Enable flag
Fig. 15 Interrupt system diagram * * * *
EI R TI
Interrupt is enabled
: Interrupt enabled state : Interrupt disabled state Fig. 13 Program example of interrupt processing
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-19
HARDWARE 4506 Group FUNCTION BLOCK OPERATIONS
(6) Interrupt control registers
* Interrupt control register V1 Interrupt enable bits of external 0, timer 1 and timer 2 are assigned to register V1. Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction can be used to transfer the contents of register V1 to register A.
* Interrupt control register V2 The A/D interrupt enable bit is assigned to register V2. Set the contents of this register through register A with the TV2A instruction. The TAV2 instruction can be used to transfer the contents of register V2 to register A.
Table 6 Interrupt control registers Interrupt control register V1 V13 V12 V11 V10 Timer 2 interrupt enable bit Timer 1 interrupt enable bit Not used External 0 interrupt enable bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : 00002 R/W
Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) (Note 2) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) (Note 2) This bit has no function, but read/write is enabled. Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) (Note 2)
Interrupt control register V2 V23 V22 V21 V20 Not used A/D interrupt enable bit Not used Not used 0 1 0 1 0 1 0 1
at reset : 00002
at RAM back-up : 00002
R/W
This bit has no function, but read/write is enabled. Interrupt disabled (SNZAD instruction is valid) Interrupt enabled (SNZAD instruction is invalid) (Note 2) This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled.
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: These instructions are equivalent to the NOP instrucion.
(7) Interrupt sequence
Interrupts only occur when the respective INTE flag, interrupt enable bits (V10, V12, V13, V22), and interrupt request flag are "1." The interrupt actually occurs 2 to 3 machine cycles after the cycle in which all three conditions are satisfied. The interrupt occurs after 3 machine cycles only when the three interrupt conditions are satisfied on execution of other than one-cycle instructions (Refer to Figure 16).
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-20
4506 Group
q When an interrupt request flag is set after its interrupt is enabled (Note 1)
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
T3 T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 Interrupt disabled state Interrupt enabled state Retaining level of system clock for 4 periods or more is necessary. Interrupt activated condition is satisfied. Flag cleared 2 to 3 machine cycles (Notes 2, 3) The program starts from the interrupt address.
Fig. 16 Interrupt sequence
f (XIN) (default mode)
f (XIN) (low-speed mode)
f (XIN) (middle-speed mode)
f (XIN) (high-speed mode)
1 machine cycle
T1
T2
System clock
Interrupt enable flag (INTE)
EI instruction execution cycle
INT
External interrupt
EXF0
Timer 1, Timer 2, and A/D interrupts
T1F, T2F ADF
FUNCTION BLOCK OPERATIONS
Notes 1: The 4506 Group operates in the default mode after system is released from reset (system clock = operation source clock divided by 8). 2: The address is stacked to the last cycle. 3: This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied.
HARDWARE
1-21
HARDWARE 4506 Group FUNCTION BLOCK OPERATIONS
EXTERNAL INTERRUPTS
The 4506 Group has the external 0 interrupt. An external interrupt request occurs when a valid waveform is input to an interrupt input pin (edge detection). The external interrupt can be controlled with the interrupt control register I1. Table 7 External interrupt activated conditions Name External 0 interrupt INT Input pin Activated condition When the next waveform is input to INT pin * Falling waveform ("H""L") * Rising waveform ("L""H") * Both rising and falling waveforms Valid waveform selection bit I11 I12
(Note) P13/INT I13
I12 Falling
0 1
One-sided edge detection circuit
I11
0
EXF0
1 Both edges detection circuit
External 0 interrupt
Rising K13
Wakeup Skip
Timer 1 count start synchronization circuit input
SNZI0 instruction
*
This symbol represents a parasitic diode on the port.
Fig. 17 External interrupt circuit structure
(1) External 0 interrupt request flag (EXF0)
External 0 interrupt request flag (EXF0) is set to "1" when a valid waveform is input to INT pin. The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (Refer to Figure 16). The state of EXF0 flag can be examined with the skip instruction (SNZ0). Use the interrupt control register V1 to select the interrupt or the skip instruction. The EXF0 flag is cleared to "0" when an interrupt occurs or when the next instruction is skipped with the skip instruction. * External 0 interrupt activated condition External 0 interrupt activated condition is satisfied when a valid waveform is input to INT pin. The valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. An example of how to use the external 0 interrupt is as follows. Set the bit 3 of register I1 to "1" for the INT pin to be in the input enabled state. Select the valid waveform with the bits 1 and 2 of register I1. Clear the EXF0 flag to "0" with the SNZ0 instruction. Set the NOP instruction for the case when a skip is performed with the SNZ0 instruction. Set both the external 0 interrupt enable bit (V10) and the INTE flag to "1." The external 0 interrupt is now enabled. Now when a valid waveform is input to the INT pin, the EXF0 flag is set to "1" and the external 0 interrupt occurs.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-22
HARDWARE 4506 Group FUNCTION BLOCK OPERATIONS
(2) External interrupt control registers
* Interrupt control register I1 Register I1 controls the valid waveform for the external 0 interrupt. Set the contents of this register through register A with the TI1A instruction. The TAI1 instruction can be used to transfer the contents of register I1 to register A. Table 8 External interrupt control register Interrupt control register I1 I13 INT pin input control bit (Note 2) 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained R/W
INT pin input disabled INT pin input enabled Falling waveform ("L" level of INT pin is recognized with the SNZI0 instruction)/"L" level Rising waveform ("H" level of INT pin is recognized with the SNZI0 instruction)/"H" level One-sided edge detected Both edges detected Disabled Enabled
I12
Interrupt valid waveform for INT pin/ return level selection bit (Note 2)
I11 I10
INT pin edge detection circuit control bit INT pin timer 1 control enable bit
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction when the bit 0 (V10) of register V1 to "0". In this time, set the NOP instruction after the SNZ0 instruction, for the case when a skip is performed with the SNZ0 instruction.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-23
HARDWARE 4506 Group FUNCTION BLOCK OPERATIONS
(3) Notes on interrupts
Note [1] on bit 3 of register I1 When the input of the INT pin is controlled with the bit 3 of register I1 in software, be careful about the following notes. * Depending on the input state of the P13/INT pin, the external 0 interrupt request flag (EXF0) may be set when the bit 3 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to "0" (refer to Figure 18) and then, change the bit 3 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to "0" after executing at least one instruction (refer to Figure 18). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 18).
Note [3] on bit 2 of register I1 When the interrupt valid waveform of the P13/INT pin is changed with the bit 2 of register I1 in software, be careful about the following notes. * Depending on the input state of the P13/INT pin, the external 0 interrupt request flag (EXF0) may be set when the bit 2 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to "0" (refer to Figure 20) and then, change the bit 2 of register I1 is changed. In addition, execute the SNZ0 instruction to clear the EXF0 flag to "0" after executing at least one instruction (refer to Figure 20). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 20).
***
LA 4 TV1A LA 8 TI1A NOP SNZ0 NOP
; (02) ; The SNZ0 instruction is valid ........... ; (12) ; Control of INT pin input is changed ........................................................... ; The SNZ0 instruction is executed (EXF0 flag cleared) ...........................................................
LA 4 TV1A LA 12 TI1A NOP SNZ0 NOP
***
; (02) ; The SNZ0 instruction is valid ........... ; (12) ; Interrupt valid waveform is changed ........................................................... ; The SNZ0 instruction is executed (EXF0 flag cleared) ...........................................................
***
: these bits are not used here. Fig. 18 External 0 interrupt program example-1 Note [2] on bit 3 of register I1 When the bit 3 of register I1 is cleared to "0" , the RAM back-up mode is selected and the input of INT pin is disabled, be careful about the following notes. * When the key-on wakeup function of port P13 is not used (register K13 = "0"), clear bits 2 and 3 of register I1 before system enters to the RAM back-up mode. (refer to Figure 19).
: these bits are not used here. Fig. 20 External 0 interrupt program example-3
LA 0 TI1A DI EPOF POF
***
; (002) ; Input of INT disabled ........................
; RAM back-up
: these bits are not used here. Fig. 19 External 0 interrupt program example-2
***
***
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-24
HARDWARE 4506 Group FUNCTION BLOCK OPERATIONS
TIMERS
The 4506 Group has the following timers. * Programmable timer The programmable timer has a reload register and enables the frequency dividing ratio to be set. It is decremented from a setting value n. When it underflows (count to n + 1), a timer interrupt request flag is set to "1," new data is loaded from the reload register, and count continues (auto-reload function).
* Fixed dividing frequency timer The fixed dividing frequency timer has the fixed frequency dividing ratio (n). An interrupt request flag is set to "1" after every n count of a count pulse.
FF16 n : Counter initial value Count starts n Reload Reload
The contents of counter
1st underflow
2nd underflow
0016 Time n+1 count Timer interrupt "1" "0" request flag An interrupt occurs or a skip instruction is executed. n+1 count
Fig. 21 Auto-reload function The 4506 Group timer consists of the following circuits. * Prescaler : frequency divider * Timer 1 : 8-bit programmable timer * Timer 2 : 8-bit programmable timer (Timers 1 and 2 have the interrupt function, respectively) * 16-bit timer Table 9 Function related timers Circuit Prescaler Timer 1 Structure Frequency divider 8-bit programmable binary down counter (link to INT input) Timer 2 8-bit programmable binary down counter * Timer 1 underflow * Prescaler output (ORCLK) * CNTR input * System clock 16-bit timer * Instruction clock 16-bit fixed dividing frequency binary down counter 65536 * Watchdog timer (The 16th bit is counted twice) 1 to 256 Count source * Instruction clock * Prescaler output (ORCLK) Frequency dividing ratio 4, 16 1 to 256 Use of output signal * Timer 1 and 2 count sources * Timer 2 count source * CNTR output * Timer 1 interrupt * CNTR output * Timer 2 interrupt Control register W1 W1 W2 W6 W2 W6 Prescaler and timers 1 and 2 can be controlled with the timer control registers W1, W2 and W6. The 16-bit timer is a free counter which is not controlled with the control register. Each function is described below.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-25
HARDWARE 4506 Group FUNCTION BLOCK OPERATIONS
System clock
Instruction clock
Prescaler
Division circuit divided by 8 divided by 4
XIN MR3, MR2 11 10 01 00 W13 0 1/4 1/16 W12 0 1
Clock generation circuit
divided by 2
Internal clock generating circuit (divided by 3)
1
ORCLK I12 Falling P13/INT I13 0 1 Rising One-sided edge detection circuit Both edges detection circuit I10 W22 I11 0 1 R (Note 1) SQ
W10 1 0
Timer 1 underflow signal
(Note 2) W11 0 1
Timer 1 (8) Reload register R1 (8)
T1AB (TAB1) (TR1AB) T1AB (TAB1)
T1F
Timer 1 interrupt
Register B Register A
Timer 1 underflow signal
W21,W20 00 01 10 11
W23 (Note 2) 0 1
Timer 2 (8) Reload register R2 (8)
(T2AB)
T2F
Timer 2 interrupt
(TAB2)
Register B Register A
(TAB2)
W60 P12/CNTR 0 1 P12 output
W61 0 1 1/2 1/2
Timer 2 underflow signal
16-bit timer (WDT)
Instruction clock
1 16 S WRST instruction (Note 3) Reset signal (Note 5) DWDT instruction + WRST instruction (Note 4) R S
WEF
Q
Data is set automatically from each reload register when timer 1 or 2 underflows (auto-reload function) Notes 1: Timer 1 count start synchronous circuit is set by the valid edge of P13/INT pin selected by bits 1 (I11) and 2 (I12) of register I1. 2: Count source is stopped by clearing to "0." 3: When the WRST instruction is executed at WDF1 flag = "1," WDF1 flag is cleared to "0" and the next instruction is skipped. When the WRST instruction is executed at Watchdog WDF1 flag = "0," skip is not executed. reset signal 4: When the DWDT and WRST instructions are executed continuously, WEF flag is cleared to "0" and reset by watchdog timer is not executed. 5: The WEF flag is set to "1" at system reset or RAM back-up mode.
WDF1
Q
R D TR Q
WDF2
Reset signal
Fig. 22 Timers structure
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-26
HARDWARE 4506 Group FUNCTION BLOCK OPERATIONS
Table 10 Timer control registers Timer control register W1 W13 W12 W11 W10 Prescaler control bit Prescaler dividing ratio selection bit Timer 1 control bit Timer 1 count start synchronous circuit control bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : 00002 R/W
Stop (state initialized) Operating Instruction clock divided by 4 Instruction clock divided by 16 Stop (state retained) Operating Count start synchronous circuit not selected Count start synchronous circuit selected
Timer control register W2 W23 W22 W21 Timer 2 count source selection bits W20 Timer 2 control bit Timer 1 count auto-stop circuit selection bit (Note 2)
at reset : 00002 0 1 0 1 W21 W20 0 0 1 1 0 1 0 1
at RAM back-up : state retained
R/W
Stop (state retained) Operating Count auto-stop circuit not selected Count auto-stop circuit selected Count source Timer 1 underflow signal Prescaler output (ORCLK) CNTR input System clock
Timer control register W6 W63 W62 W61 W60 Not used Not used CNTR output selection bit P12/CNTR function selection bit 0 1 0 1 0 1 0 1
at reset : 00002
at RAM back-up : state retained
R/W
This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. Timer 1 underflow signal divided by 2 output Timer 2 underflow signal divided by 2 output P12(I/O)/CNTR input (Note 3) P12 (input)/CNTR input/output (Note 3)
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: This function is valid only when the timer 1 count start synchronization circuit is selected. 3: CNTR input is valid only when CNTR input is selected as the timer 2 count source.
(1) Timer control registers
* Timer control register W1 Register W1 controls the count operation of timer 1, the selection of count start synchronous circuit, and the frequency dividing ratio and count operation of prescaler. Set the contents of this register through register A with the TW1A instruction. The TAW1 instruction can be used to transfer the contents of register W1 to register A. * Timer control register W2 Register W2 controls the selection of timer 1 count auto-stop circuit, and the count operation and count source of timer 2. Set the contents of this register through register A with the TW2A instruction. The TAW2 instruction can be used to transfer the contents of register W2 to register A.
* Timer control register W6 Register W6 controls the P12/CNTR pin function and the selection of CNTR output. Set the contents of this register through register A with the TW6A instruction. The TAW6 instruction can be used to transfer the contents of register W6 to register A..
(2) Prescaler
Prescaler is a frequency divider. Its frequency dividing ratio can be selected. The count source of prescaler is the instruction clock. Use the bit 2 of register W1 to select the prescaler dividing ratio and the bit 3 to start and stop its operation. Prescaler is initialized, and the output signal (ORCLK) stops when the bit 3 of register W1 is cleared to "0."
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-27
HARDWARE 4506 Group FUNCTION BLOCK OPERATIONS
(3) Timer 1 (interrupt function)
Timer 1 is an 8-bit binary down counter with the timer 1 reload register (R1). Data can be set simultaneously in timer 1 and the reload register (R1) with the T1AB instruction. Stop counting and then execute the T1AB instruction to set data to timer 1. Data can be written to reload register (R1) with the TR1AB instruction. When writing data to reload register R1 with the TR1AB instruction, the downcount after the underflow is started from the setting value of reload register R1. Timer 1 starts counting after the following process; set data in timer 1, and set the bit 1 of register W1 to "1." However, INT pin input can be used as the start trigger for timer 1 count operation by setting the bit 0 of register W1 to "1." Also, in this time, the auto-stop function by timer 1 underflow can be performed by setting the bit 2 of register W2 to "1." When a value set is n, timer 1 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 1 underflows (the next count pulse is input after the contents of timer 1 becomes "0"), the timer 1 interrupt request flag (T1F) is set to "1," new data is loaded from reload register R1, and count continues (auto-reload function). Data can be read from timer 1 with the TAB1 instruction. When reading the data, stop the counter and then execute the TAB1 instruction.
(6) Count start synchronization circuit (timer 1)
Timer 1 has the count start synchronous circuit which synchronizes the input of INT pin, and can start the timer count operation. Timer 1 count start synchronous circuit function is selected by setting the bit 0 of register W1 to "1." The control by INT pin input can be performed by setting the bit 0 of register I1 to "1." The count start synchronous circuit is set by level change ("H""L" or "L""H") of INT pin input. This valid waveform is selected by bits 1 (I11) and 2 (I12) of register I1 as follows; * I11 = "0": Synchronized with one-sided edge (falling or rising) * I11 = "1": Synchronized with both edges (both falling and rising) When register I11="0" (synchronized with the one-sided edge), the rising or falling waveform can be selected by the bit 2 of register I1; * I12 = "0": Falling waveform * I12 = "1": Rising waveform When timer 1 count start synchronous circuit is used, the count start synchronous circuit is set, the count source is input to each timer by inputting valid waveform to INT pin. Once set, the count start synchronous circuit is cleared by clearing the bit I10 to "0" or reset. However, when the count auto-stop circuit is selected (register W22 = "1"), the count start synchronous circuit is cleared (auto-stop) at the timer 1 underflow.
(7) Count auto-stop circuit (timer 1) (4) Timer 2 (interrupt function)
Timer 2 is an 8-bit binary down counter with the timer 2 reload register (R2). Data can be set simultaneously in timer 2 and the reload register (R2) with the T2AB instruction. Stop counting and then execute the T2AB instruction to set data to timer 2. Timer 2 starts counting after the following process; set data in timer 2, select the count source with the bits 0 and 1 of register W2, and set the bit 3 of register W2 to "1." When a value set is n, timer 2 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 2 underflows (the next count pulse is input after the contents of timer 2 becomes "0"), the timer 2 interrupt request flag (T2F) is set to "1," new data is loaded from reload register R2, and count continues (auto-reload function). Data can be read from timer 2 with the TAB2 instruction. When reading the data, stop the counter and then execute the TAB2 instruction. Timer 1 has the count auto-stop circuit which is used to stop timer 1 automatically by the timer 1 underflow when the count start synchronous circuit is used. The count auto-stop cicuit is valid by setting the bit 2 of register W2 to "1". It is cleared by the timer 1 underflow and the count source to timer 1 is stopped. This function is valid only when the timer 1 count start synchronous circuit is selected.
(5) Timer interrupt request flags (T1F, T2F)
Each timer interrupt request flag is set to "1" when each timer underflows. The state of these flags can be examined with the skip instructions (SNZT1, SNZT2). Use the interrupt control register V1 to select an interrupt or a skip instruction. An interrupt request flag is cleared to "0" when an interrupt occurs or when the next instruction is skipped with a skip instruction.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-28
HARDWARE 4506 Group FUNCTION BLOCK OPERATIONS
(8) Timer input/output pin (P12/CNTR pin)
CNTR pin is used to input the timer 2 count source and output the timer 1 and timer 2 underflow signal divided by 2. The P12/CNTR pin function can be selected by bit 0 of register W6. The CNTR output signal can be selected by bit 1 of register W6. When the CNTR input is selected for timer 2 count source, timer 2 counts the falling waveform of CNTR input.
(9) Precautions
Note the following for the use of timers. *Prescaler Stop the prescaler operation to change its frequency dividing ratio. *Count source Stop timer 1 or 2 counting to change its count source. *Reading the count value Stop timer 1 or 2 counting and then execute the TAB1 or TAB2 instruction to read its data. *Writing to the timer Stop timer 1 or 2 counting and then execute the T1AB or T2AB instruction to write its data. *Writing to reload register R1 When writing data to reload register R1 while timer 1 is operating, avoid a timing when timer 1 underflows.
CNTR input (Note) Timer 2 count 0316 0216 0116 0016 FF16 FE16
Timer 2 interrupt request flag (T2F)
Note: This is an example when "FF16" is set to timer 2 reload register R2L.
Fig. 23 Count timing diagram at CNTR input
* Timer 1 and timer 2 count start timing and count time when operation starts Count starts from the first rising edge of the count source (2) after timer 1 and timer 2 operations start (1). Time to first underflow (3) is shorter (for up to 1 period of the count source) than time among next underflow (4) by the timing to start the timer and count source operations after count starts. When selecting CNTR input as the count source of timer 2, timer 2 operates synchronizing with the falling edge of CNTR input.
(2) Count Source Count Source (CNTR input) Timer Value 3 2 1 0 3 2 1 0 3 2
Timer Underflow Signal (3) (1) Timer (4)
Fig. 24 Timer count start timing and count time when operation starts (T1, T2)
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-29
HARDWARE 4506 Group FUNCTION BLOCK OPERATIONS
WATCHDOG TIMER
Watchdog timer provides a method to reset the system when a program run-away occurs. Watchdog timer consists of timer WDT(16-bit binary counter), watchdog timer enable flag (WEF), and watchdog timer flags (WDF1, WDF2). The timer WDT downcounts the instruction clocks as the count source from "FFFF16" after system is released from reset. After the count is started, when the timer WDT underflow occurs (after the count value of timer WDT reaches "FFFF16," the next count pulse is input), the WDF1 flag is set to "1." If the WRST instruction is never executed until the timer WDT underflow occurs (until timer WDT counts 65534), WDF2 flag is set to "1," and the RESET pin outputs "L" level to reset the microcomputer. Execute the WRST instruction at each period of 65534 machine cycle or less by software when using watchdog timer to keep the microcomputer operating normally. When the WEF flag is set to "1" after system is released from reset, the watchdog timer function is valid. When the DWDT instruction and the WRST instruction are executed continuously, the WEF flag is cleared to "0" and the watchdog timer function is invalid. The WEF flag is set to "1" at system reset or RAM back-up mode. The WRST instruction has the skip function. When the WRST instruction is executed while the WDF1 flag is "1", the WDF1 flag is cleared to "0" and the next instruction is skipped. When the WRST instruction is executed while the WDF1 flag is "0", the next instruction is not skipped. The skip function of the WRST instruction can be used even when the watchdog timer function is invalid.
FFFF16 Value of 16-bit timer (WDT) 000016 WDF1 flag
65534 count (Note) WDF2 flag
RESET pin output Reset released WRST instruction executed (skip executed) System reset
After system is released from reset (= after program is started), timer WDT starts count down. When timer WDT underflow occurs, WDF1 flag is set to "1." When the WRST instruction is executed, WDF1 flag is cleared to "0," the next instruction is skipped. When timer WDT underflow occurs while WDF1 flag is "1," WDF2 flag is set to "1" and the watchdog reset signal is output. The output transistor of RESET pin is turned "ON" by the watchdog reset signal and system reset is executed. Note: The number of count is equal to the number of machine cycle because the count source of watchdog timer is the instruction clock.
Fig. 25 Watchdog timer function
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-30
HARDWARE 4506 Group FUNCTION BLOCK OPERATIONS
When the watchdog timer is used, clear the WDF1 flag at the period of 65534 machine cycles or less with the WRST instruction. When the watchdog timer is not used, execute the DWDT instruction and the WRST instruction continuously (refer to Figure 26). The watchdog timer is not stopped with only the DWDT instruction. The contents of WDF1 flag and timer WDT are initialized at the RAM back-up mode. When using the watchdog timer and the RAM back-up mode, initialize the WDF1 flag with the WRST instruction just before the microcomputer enters the RAM back-up state (refer to Figure 27) The watchdog timer function is valid after system is returned from the RAM back-up. When not using the watchdog timer function, execute the DWDT instruction and the WRST instruction continuously every system is returned from the RAM back-up, and stop the watchdog timer function.
WRST
***
; WDF1 flag cleared
DI DWDT WRST
***
; Watchdog timer function enabled/disabled ; WEF and WDF1 flags cleared
Fig. 26 Program example to start/stop watchdog timer
WRST ; WDF1 flag cleared NOP DI ; Interrupt disabled EPOF ; POF instruction enabled POF2 Oscillation stop (RAM back-up mode)
Fig. 27 Program example to enter the RAM back-up mode when using the watchdog timer
***
***
***
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-31
HARDWARE 4506 Group FUNCTION BLOCK OPERATIONS
A/D CONVERTER
The 4506 Group has a built-in A/D conversion circuit that performs conversion by 10-bit successive comparison method. Table 11 shows the characteristics of this A/D converter. This A/D converter can also be used as an 8-bit comparator to compare analog voltages input from the analog input pin with preset values.
Table 11 A/D converter characteristics Characteristics Parameter Successive comparison method Conversion format Resolution Relative accuracy Conversion speed Analog input pin 10 bits Linearity error: 2LSB Differential non-linearity error: 0.9LSB 46.5 s (High-speed mode at 4.0 MHz oscillation frequency) 2
Register B (4)
Register A (4) 4 IAP2 (P20, P21) OP2A (P20, P21) TAQ1 TQ1A 2
Q13 Q12 Q11 Q10
4 4
4 8 TABAD
8 TADAB
TALA Instruction clock 1/6
2 Q13
0
A/D control circuit
2-channel multi-plexed analog switch
1
ADF (1)
A/D interrupt
P20/AIN0 P21/AIN1
1
Comparator
0
Successive comparison register (AD) (10) 10 10
1
Q13 8
0 1
Q13
DAC operation signal
0
1
Q13
DAC DA converter
(Note 1)
8 8 VDD 8
VSS Comparator register (8)
(Note 2)
Notes 1: This switch is turned ON only when A/D converter is operating and generates the comparison voltage. 2: Writing/reading data to the comparator register is possible only in the comparator mode (Q13=1). The value of the comparator register is retained even when the mode is switched to the A/D conversion mode (Q13=0) because it is separated from the successive comparison register (AD). Also, the resolution in the comparator mode is 8 bits because the comparator register consists of 8 bits.
Fig. 28 A/D conversion circuit structure
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-32
HARDWARE 4506 Group FUNCTION BLOCK OPERATIONS
Table 12 A/D control registers
A/D control register Q1 Q13 Q12 Q11 Analog input pin selection bits Q10 A/D operation mode selection bit Not used at reset : 00002 0 1 0 1 Q11 Q10 0 0 0 1 1 0 1 1 A/D conversion mode Comparator mode This bit has no function, but read/write is enabled. Selected pins AIN0 AIN1 Not available Not available at RAM back-up : state retained R/W
Note: "R" represents read enabled, and "W" represents write enabled.
(1) Operating at A/D conversion mode
The A/D conversion mode is set by setting the bit 3 of register Q1 to "0."
(6) Operation description
A/D conversion is started with the A/D conversion start instruction (ADST). The internal operation during A/D conversion is as follows: When the A/D conversion starts, the register AD is cleared to "00016." Next, the topmost bit of the register AD is set to "1," and the comparison voltage Vref is compared with the analog input voltage VIN. When the comparison result is Vref < VIN, the topmost bit of the register AD remains set to "1." When the comparison result is Vref > VIN, it is cleared to "0." The 4506 Group repeats this operation to the lowermost bit of the register AD to convert an analog value to a digital value. A/D conversion stops after 62 machine cycles (46.5 s when f(XIN) = 4.0 MHz in high-speed mode) from the start, and the conversion result is stored in the register AD. An A/D interrupt activated condition is satisfied and the ADF flag is set to "1" as soon as A/D conversion completes (Figure 29).
(2) Successive comparison register AD
Register AD stores the A/D conversion result of an analog input in 10-bit digital data format. The contents of the high-order 8 bits of this register can be stored in register B and register A with the TABAD instruction. The contents of the low-order 2 bits of this register can be stored into the high-order 2 bits of register A with the TALA instruction. However, do not execute these instructions during A/D conversion. When the contents of register AD is n, the logic value of the comparison voltage Vref generated from the built-in DA converter can be obtained with the reference voltage VDD by the following formula: Logic value of comparison voltage Vref Vref =
VDD n 1024
n: The value of register AD (n = 0 to 1023)
(3) A/D conversion completion flag (ADF)
A/D conversion completion flag (ADF) is set to "1" when A/D conversion completes. The state of ADF flag can be examined with the skip instruction (SNZAD). Use the interrupt control register V2 to select the interrupt or the skip instruction. The ADF flag is cleared to "0" when the interrupt occurs or when the next instruction is skipped with the skip instruction.
(4) A/D conversion start instruction (ADST)
A/D conversion starts when the ADST instruction is executed. The conversion result is automatically stored in the register AD.
(5) A/D control register Q1
Register Q1 is used to select the operation mode and one of analog input pins.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-33
HARDWARE 4506 Group FUNCTION BLOCK OPERATIONS
Table 13 Change of successive comparison register AD during A/D conversion At starting conversion 1st comparison 2nd comparison 3rd comparison After 10th comparison completes 1: 1st comparison result 3: 3rd comparison result 9: 9th comparison result Change of successive comparison register AD
-------------
Comparison voltage (Vref) value VDD 2 VDD 2 VDD 2 VDD VDD 4 VDD VDD 4

1 1 1
0 1 2
0 0 1
-------------
0 0 0
0 0 0
0 0 0
-------------------------------------------------------------

8 VDD 1024
A/D conversion result
-------------
1
2
3
-------------
-----
8
9
A
2
2: 2nd comparison result 8: 8th comparison result A: 10th comparison result
(7) A/D conversion timing chart
Figure 29 shows the A/D conversion timing chart.
ADST instruction 62 machine cycles A/D conversion completion flag (ADF) DAC operation signal
Fig. 29 A/D conversion timing chart
(8) How to use A/D conversion
How to use A/D conversion is explained using as example in which the analog input from P21/AIN1 pin is A/D converted, and the highorder 4 bits of the converted data are stored in address M(Z, X, Y) = (0, 0, 0), the middle-order 4 bits in address M(Z, X, Y) = (0, 0, 1), and the low-order 2 bits in address M(Z, X, Y) = (0, 0, 2) of RAM. The A/D interrupt is not used in this example. Select the AIN1 pin function and A/D conversion mode with the register Q1 (refer to Figure 30). Execute the ADST instruction and start A/D conversion. Examine the state of ADF flag with the SNZAD instruction to determine the end of A/D conversion. Transfer the low-order 2 bits of converted data to the high-order 2 bits of register A (TALA instruction). Transfer the contents of register A to M (Z, X, Y) = (0, 0, 2). Transfer the high-order 8 bits of converted data to registers A and B (TABAD instruction). Transfer the contents of register A to M (Z, X, Y) = (0, 0, 1). Transfer the contents of register B to register A, and then, store into M(Z, X, Y) = (0, 0, 0).
(Bit 3)
(Bit 0)
0
0
0
1
A/D control register Q1
AIN1 pin selected A/D conversion mode
Fig. 30 Setting registers
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-34
HARDWARE 4506 Group FUNCTION BLOCK OPERATIONS
(9) Operation at comparator mode
The A/D converter is set to comparator mode by setting bit 3 of the register Q1 to "1." Below, the operation at comparator mode is described.
(12) Comparator operation start instruction (ADST instruction)
In comparator mode, executing ADST starts the comparator operating. The comparator stops 8 machine cycles after it has started (6 s at f(XIN) = 4.0 MHz in high-speed mode). When the analog input voltage is lower than the comparison voltage, the ADF flag is set to "1."
(10) Comparator register
In comparator mode, the built-in DA comparator is connected to the 8-bit comparator register as a register for setting comparison voltages. The contents of register B is stored in the high-order 4 bits of the comparator register and the contents of register A is stored in the low-order 4 bits of the comparator register with the TADAB instruction. When changing from A/D conversion mode to comparator mode, the result of A/D conversion (register AD) is undefined. However, because the comparator register is separated from register AD, the value is retained even when changing from comparator mode to A/D conversion mode. Note that the comparator register can be written and read at only comparator mode. If the value in the comparator register is n, the logic value of comparison voltage Vref generated by the built-in DA converter can be determined from the following formula: Logic value of comparison voltage Vref Vref = VDD 256 n
(13) Notes for the use of A/D conversion 1
Note the following when using the analog input pins also for port P2 function: * Selection of analog input pins Even when P20/AIN0, P21/AIN1 are set to pins for analog input, they continue to function as port P2 input/output. Accordingly, when any of them are used as I/O port and others are used as analog input pins, make sure to set the outputs of pins that are set for analog input to "1." Also, the port input function of the pin functions as an analog input is undefined. * TALA instruction When the TALA instruction is executed, the low-order 2 bits of register AD is transferred to the high-order 2 bits of register A, simultaneously, the low-order 2 bits of register A is "0."
(14) Notes for the use of A/D conversion 2
Do not change the operating mode (both A/D conversion mode and comparator mode) of A/D converter with the bit 3 of register Q1 while the A/D converter is operating. When the operating mode of A/D converter is changed from the comparator mode to A/D conversion mode with the bit 3 of register Q1, note the following; * Clear the bit 2 of register V2 to "0" to change the operating mode of the A/D converter from the comparator mode to A/D conversion mode with the bit 3 of register Q1. * The A/D conversion completion flag (ADF) may be set when the operating mode of the A/D converter is changed from the comparator mode to the A/D conversion mode. Accordingly, set a value to the bit 3 of register Q1, and execute the SNZAD instruction to clear the ADF flag.
n: The value of register AD (n = 0 to 255)
(11) Comparison result store flag (ADF)
In comparator mode, the ADF flag, which shows completion of A/D conversion, stores the results of comparing the analog input voltage with the comparison voltage. When the analog input voltage is lower than the comparison voltage, the ADF flag is set to "1." The state of ADF flag can be examined with the skip instruction (SNZAD). Use the interrupt control register V2 to select the interrupt or the skip instruction. The ADF flag is cleared to "0" when the interrupt occurs or when the next instruction is skipped with the skip instruction.
ADST instruction 8 machine cycles Comparison result store flag(ADF) DAC operation signal
Comparator operation completed. (The value of ADF is determined)
Fig. 31 Comparator operation timing chart
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-35
HARDWARE 4506 Group FUNCTION BLOCK OPERATIONS
(15) Definition of A/D converter accuracy
The A/D conversion accuracy is defined below (refer to Figure 32). * Relative accuracy Zero transition voltage (V0T) This means an analog input voltage when the actual A/D conversion output data changes from "0" to "1." Full-scale transition voltage (VFST) This means an analog input voltage when the actual A/D conversion output data changes from "1023" to "1022." Linearity error This means a deviation from the line between V0T and VFST of a converted value between V0T and VFST. Differential non-linearity error This means a deviation from the input potential difference required to change a converter value between V0T and VFST by 1 LSB at the relative accuracy. * Absolute accuracy This means a deviation from the ideal characteristics between 0 to VDD of actual A/D conversion characteristics.
Vn: Analog input voltage when the output data changes from "n" to "n+1" (n = 0 to 1022) * 1LSB at relative accuracy VFST-V0T (V) 1022 VDD 1024
* 1LSB at absolute accuracy
(V)
Output data
1023 1022
Full-scale transition voltage (VFST)
Differential non-linearity error = b-a [LSB] a Linearity error = c [LSB] a
b a
n+1 n
Actual A/D conversion characteristics c a: 1LSB by relative accuracy b: Vn+1-Vn c: Difference between ideal Vn and actual Vn
Ideal line of A/D conversion between V0-V1022
1 0
V0 V1 Zero transition voltage (V0T)
Vn
Vn+1
V1022 Analog voltage
VDD
Fig. 32 Definition of A/D conversion accuracy
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-36
HARDWARE 4506 Group FUNCTION BLOCK OPERATIONS
RESET FUNCTION
System reset is performed by applying "L" level to RESET pin for 1 machine cycle or more when the following condition is satisfied; the value of supply voltage is the minimum value or more of the recommended operating conditions. Then when "H" level is applied to RESET pin, software starts from address 0 in page 0.
f(XIN)
RESET On-chip oscillator (internal oscillator)
is counted 5359 times.
Program starts (address 0 in page 0)
Fig. 33 Reset release timing
Reset input
=
On-chip oscillator (internal oscillator) is
1 machine cycle or more
counted 5359 times.
0.85VDD RESET 0.3VDD
Program starts (address 0 in page 0)
(Note)
Note: Keep the value of supply voltage to the minimum value or more of the recommended operating conditions.
Fig. 34 RESET pin input waveform and reset operation
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-37
HARDWARE 4506 Group FUNCTION BLOCK OPERATIONS
(1) Power-on reset
Reset can be performed automatically at power on (power-on reset) by connecting a diode and a capacitor to RESET pin. Connect RESET pin and the external circuit at the shortest distance.
VDD
VDD RESET pin voltage
Pull-up transistor Internal reset signal Watchdog timer output
(Note 1)
RESET
pin
(Note 2)
Reset state Internal reset signal
WEF
Reset released Power-on Notes 1: This symbol represents a parasitic diode. 2: Applied potential to RESET pin must be VDD or less.
Fig. 35 Structure of reset pin and its peripherals, and power-on reset operation Table 14 Port state at reset Name D0, D1 D2/C, D3/K P00, P01, P02, P03 P10, P11, P12/CNTR, P13/INT P20/AIN0, P21/AIN1
Notes 1: Output latch is set to "1." 2: Pull-up transistor is turned OFF.
Function D0, D1 D2, D3 P00-P03 P10-P13 P20, P21 High-impedance (Note 1) High-impedance (Notes 1, 2) High-impedance (Notes 1, 2) High-impedance (Notes 1, 2) High-impedance (Notes 1, 2)
State
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-38
HARDWARE 4506 Group FUNCTION BLOCK OPERATIONS
(2) Internal state at reset
Figure 36 shows internal state at reset (they are the same after system is released from reset). The contents of timers, registers, flags and RAM except shown in Figure 36 are undefined, so set the initial value to them.
* Program counter (PC) .......................................................................................................... 0 00000 Address 0 in page 0 is set to program counter. * Interrupt enable flag (INTE) .................................................................................................. 0 * Power down flag (P) ............................................................................................................. 0 * External 0 interrupt request flag (EXF0) .............................................................................. 0 * Interrupt control register V1 .................................................................................................. 0 000 * Interrupt control register V2 .................................................................................................. 0 000 * Interrupt control register I1 ................................................................................................... 0 000 * Timer 1 interrupt request flag (T1F) ..................................................................................... 0 * Timer 2 interrupt request flag (T2F) ..................................................................................... 0 * Watchdog timer flags (WDF1, WDF2) .................................................................................. 0 * Watchdog timer enable flag (WEF) ...................................................................................... 1 * Timer control register W1 ..................................................................................................... 0 000 * Timer control register W2 ..................................................................................................... 0 000 * Timer control register W6 ..................................................................................................... 0 000 * Clock control register MR ..................................................................................................... 0 110 * Key-on wakeup control register K0 ...................................................................................... 0 000 * Key-on wakeup control register K1 ...................................................................................... 0 000 * Key-on wakeup control register K2 ...................................................................................... 0 000 * Pull-up control register PU0 ................................................................................................. 0 000 * Pull-up control register PU1 ................................................................................................. 0 000 * Pull-up control register PU2 ................................................................................................. 0 000 * A/D conversion completion flag (ADF) ................................................................................. 0 * A/D control register Q1 ......................................................................................................... 0 000 * Carry flag (CY) ...................................................................................................................... 0 * Register A ............................................................................................................................. 0 000 * Register B ............................................................................................................................. 0 000 * Register D ............................................................................................................................. * Register E ............................................................................................................................. * Register X ............................................................................................................................. 0 000 * Register Y ............................................................................................................................. 0 000 * Register Z ............................................................................................................................. * Stack pointer (SP) ................................................................................................................ 1 11 * Oscillation clock ..................................................................... On-chip oscillator (operating) * Ceramic resonator circuit ..................................................................................... Operating * RC oscillation circuit ...................................................................................................... Stop
0
0
0
0
0
0
0
0
(Interrupt disabled)
(Interrupt disabled) (Interrupt disabled)
(Prescaler and timer 1 stopped) (Timer 2 stopped)
"" represents undefined.
Fig. 36 Internal state at reset
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-39
HARDWARE 4506 Group FUNCTION BLOCK OPERATIONS
RAM BACK-UP MODE
The 4506 Group has the RAM back-up mode. When the POF2 instruction is executed continuously after the EPOF instruction, system enters the RAM back-up state. The POF2 instruction is equal to the NOP instruction when the EPOF instruction is not executed before the POF2 instruction. As oscillation stops retaining RAM, the function of reset circuit and states at RAM back-up mode, current dissipation can be reduced without losing the contents of RAM. Table 15 shows the function and states retained at RAM back-up. Figure 37 shows the state transition.
Table 15 Functions and states retained at RAM back-up Function Program counter (PC), registers A, B, carry flag (CY), stack pointer (SP) (Note 2) Contents of RAM Port level Selected oscillation circuit Timer control register W1 Timer control registers W2, W6 Clock control register MR Interrupt control registers V1, V2 Interrupt control register I1 Timer 1 function Timer 2 function A/D conversion function A/D control register Q1 Pull-up control registers PU0 to PU2 Key-on wakeup control registers K0 to K2 External 0 interrupt request flag (EXF0) Timer 1 interrupt request flag (T1F) Timer 2 interrupt request flag (T2F) Watchdog timer flags (WDF1) Watchdog timer enable flag (WEF) 16-bit timer (WDT) A/D conversion completion flag (ADF) Interrupt enable flag (INTE) RAM back-up O (Note 5) O O O (Note 3) O O O (Note 3) (Note 4) (Note 4)
(1) Identification of the start condition
Warm start (return from the RAM back-up state) or cold start (return from the normal reset state) can be identified by examining the state of the power down flag (P) with the SNZP instruction.
(2) Warm start condition
When the external wakeup signal is input after the system enters the RAM back-up state by executing the EPOF instruction and POF2 instruction continuously, the CPU starts executing the program from address 0 in page 0. In this case, the P flag is "1."
(3) Cold start condition
The CPU starts executing the program from address 0 in page 0 when; * reset pulse is input to RESET pin, or * reset by watchdog timer is performed, or In this case, the P flag is "0."
Notes 1: "O" represents that the function can be retained, and "" represents that the function is initialized. Registers and flags other than the above are undefined at RAM back-up, and set an initial value after returning. 2: The stack pointer (SP) points the level of the stack register and is initialized to "7" at RAM back-up. 3: The state of the timer is undefined. 4: Initialize the watchdog timer flag WDF1 with the WRST instruction, and then execute the POF2 instruction. 5: As for the D2/C pin, the output latch of port C is set to "1" at the RAM back-up. However, the output latch of port D2 is retained. As for the other ports, their output levels are retained at the RAM back-up.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-40
HARDWARE 4506 Group FUNCTION BLOCK OPERATIONS
(4) Return signal
An external wakeup signal is used to return from the RAM back-up mode because the oscillation is stopped. Table 16 shows the return condition for each return source.
(5) Control registers
* Key-on wakeup control register K0 Register K0 controls the port P0 key-on wakeup function. Set the contents of this register through register A with the TK0A instruction. In addition, the TAK0 instruction can be used to transfer the contents of register K0 to register A. * Key-on wakeup control register K1 Register K1 controls the port P1 key-on wakeup function. Set the contents of this register through register A with the TK1A instruction. In addition, the TAK1 instruction can be used to transfer the contents of register K0 to register A. * Key-on wakeup control register K2 Register K2 controls the ports P2, D2/C and D3/K key-on wakeup function. Set the contents of this register through register A with the TK2A instruction. In addition, the TAK2 instruction can be used to transfer the contents of register K2 to register A.
* Pull-up control register PU0 Register PU0 controls the ON/OFF of the port P0 pull-up transistor. Set the contents of this register through register A with the TPU0A instruction. * Pull-up control register PU1 Register PU1 controls the ON/OFF of the port P1 pull-up transistor. Set the contents of this register through register A with the TPU1A instruction. * Pull-up control register PU2 Register PU2 controls the ON/OFF of the ports P2, D2/C and D3/ K pull-up transistor. Set the contents of this register through register A with the TPU2A instruction. * Interrupt control register I1 Register I1 controls the valid waveform of the external 0 interrupt, the input control of INT pin and the return input level. Set the contents of this register through register A with the TI1A instruction. In addition, the TAI1 instruction can be used to transfer the contents of register I1 to register A.
External wakeup signal
Table 16 Return source and return condition Return source Return condition Port P0 Return by an external "L" level input. Port P1 (Note) Port P2 Ports D2/C, D3/K Port P13/INT (Note) Return by an external "H" level or "L" level input. The return level can be selected with the bit 2 (I12) of register I1. When the return level is input, the EXF0 flag is not set.
Remarks The key-on wakeup function can be selected by one port unit. Set the port using the key-on wakeup function to "H" level before going into the RAM back-up state.
Select the return level ("L" level or "H" level) with the bit 2 of register I1 according to the external state before going into the RAM back-up state.
Note: When the bit 3 (K13) of register K1 is "0", the key-on wakeup of the INT pin is valid ("H" or "L" level). It is "1", the key-on wakeup of port P13 is valid ("L" level).
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-41
HARDWARE 4506 Group FUNCTION BLOCK OPERATIONS
B
Operating
Operation source clock: ceramic resonator Key-on wakeup On-chip oscillator: stop RC oscillation circuit: stop CMCK instruction execution (Note 3) (Stabilizing time b ) POF2 instruction execution
E
RAM back-up
(All functions of microcomputer stop)
A
Operating
Reset (Stabilizing time a ) Operation source clock: on-chip oscillator clock Ceramic resonator: operating (Note 2) RC oscillation circuit: stop CRCK instruction execution (Note 3) Key-on wakeup (Stabilizing time a ) POF2 instruction execution
C
Operating
Operation source clock: RC oscillation On-chip oscillator: stop Ceramic resonator: stop
POF2 instruction execution
Key-on wakeup (Stabilizing time c ) Operation source clock: stop
Stabilizing time a : Microcomputer starts its operation after counting the on-chip oscillator clock 5359 times by hardware. Stabilizing time b : Microcomputer starts its operation after counting the f(XIN) 5359 times by hardware. Stabilizing time c : Microcomputer starts its operation after counting the f(XIN) 165 times by hardware. Notes 1: Continuous execution of the EPOF instruction and POF2 instruction is required to go into the RAM back-up state. 2: Through the ceramic resonator is operating, the on-chip oscillator clock is selected as the operation source clock. 3: The oscillator clock corresponding to each instruction is selected as the operation source clock, and the on-chip oscillator is stopped.
Fig. 37 State transition
EPOF + POF2 instruction instruction
Power down flag P S Q
Program start P = "1" ? No Cold start Yes
Reset input
R
q Set source
*******
EPOF instruction + POF2 instruction
Warm start
q Clear source * * * * * * Reset input
Fig. 38 Set source and clear source of the P flag
Fig. 39 Start condition identified example using the SNZP instruction
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-42
HARDWARE 4506 Group FUNCTION BLOCK OPERATIONS
Table 17 Key-on wakeup control register Key-on wakeup control register K0 K03 K02 K01 K00 Port P03 key-on wakeup control bit Port P02 key-on wakeup control bit Port P01 key-on wakeup control bit Port P00 key-on wakeup control bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : state retained R/W
Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used
Key-on wakeup control register K1 K13 K12 K11 K10 Port P13/INT key-on wakeup control bit Port P12/CNTR key-on wakeup control bit Port P11 key-on wakeup control bit Port P10 key-on wakeup control bit 0 1 0 1 0 1 0 1
at reset : 00002
at RAM back-up : state retained
R/W
P13 key-on wakeup not used/INT pin key-on wakeup used P13 key-on wakeup used/INT pin key-on wakeup not used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used
Key-on wakeup control register K2 K23 K22 K21 K20 Port D3/K key-on wakeup control bit Port D2/C key-on wakeup control bit Port P21/AIN1 key-on wakeup control bit Port P20/AIN0 key-on wakeup control bit 0 1 0 1 0 1 0 1
at reset : 00002
at RAM back-up : state retained
R/W
Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used
Note: "R" represents read enabled, and "W" represents write enabled.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-43
HARDWARE 4506 Group FUNCTION BLOCK OPERATIONS
Table 18 Pull-up control register and interrupt control register Pull-up control register PU0 PU03 PU02 PU01 PU00 Port P03 pull-up transistor control bit Port P02 pull-up transistor control bit Port P01 pull-up transistor control bit Port P00 pull-up transistor control bit Pull-up control register PU1 PU13 PU12 PU11 PU10 Port P13/INT pull-up transistor control bit Port P12/CNTR pull-up transistor control bit Port P11 pull-up transistor control bit Port P10 pull-up transistor control bit 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 at reset : 00002 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON at reset : 00002 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON at RAM back-up : state retained W at RAM back-up : state retained W
Pull-up control register PU2 PU23 PU22 PU21 PU20 Port D3/K pull-up transistor control bit Port D2/C pull-up transistor control bit Port P21/AIN1 pull-up transistor control bit Port P20/AIN0 pull-up transistor control bit 0 1 0 1 0 1 0 1
at reset : 00002 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON
at RAM back-up : state retained
W
Interrupt control register I1 I13 INT pin input control bit (Note 2) 0 1 0 1 0 1 0 1
at reset : 00002
at RAM back-up : state retained
R/W
INT pin input disabled INT pin input enabled Falling waveform ("L" level of INT pin is recognized with the SNZI0 instruction)/"L" level Rising waveform ("H" level of INT pin is recognized with the SNZI0 instruction)/"H" level One-sided edge detected Both edges detected Disabled Enabled
I12
Interrupt valid waveform for INT pin/ return level selection bit (Note 2)
I11 I10
INT pin edge detection circuit control bit INT pin timer 1 control enable bit
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction when the bit 0 (V10) of register V1 to "0". In this time, set the NOP instruction after the SNZ0 instruction, for the case when a skip is performed with the SNZ0 instruction.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-44
HARDWARE 4506 Group FUNCTION BLOCK OPERATIONS
CLOCK CONTROL
The clock control circuit consists of the following circuits. * On-chip oscillator (internal oscillator) * Ceramic resonator * RC oscillation circuit * Multi-plexer (clock selection circuit) * Frequency divider * Internal clock generating circuit
The system clock and the instruction clock are generated as the source clock for operation by these circuits. Figure 40 shows the structure of the clock control circuit. The 4506 Group operates by the on-chip oscillator clock (f(RING)) which is the internal oscillator after system is released from reset. Also, the ceramic resonator or the RC oscillation can be used for the source oscillation (f(XIN)) of the 4506 Group. The CMCK instruction or CRCK instruction is executed to select the ceramic resonator or RC oscillator, respectively.
Division circuit divided by 8 divided by 4
MR3, MR2 11 10 01 00
System clock Internal clock generation circuit (divided by 3)
On-chip oscillator (internal oscillator) (Note 1)
Instruction clock Counter
divided by 2
Multiplexer
QS QR
RC oscillation circuit
QS R XIN XOUT CRCK instruction
Wait time (Note 2) control circuit
Program start signal
Ceramic resonator circuit
QS R QS R CMCK instruction RESET pin
Key-on wakeup signal
EPOF instruction + POF2 instruction
Notes 1: System operates by the on-chip oscillator clock (f(RING)) until the CMCK or CRCK instruction is executed after system is released from reset. 2: The wait time control circuit is used to generate the time required to stabilize the f(XIN) oscillation. After the certain oscillation stabilizing wait time elapses, the program start signal is output. This circuit operates when system is released from reset or returned from RAM back-up. Fig. 40 Clock control circuit structure
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-45
HARDWARE 4506 Group FUNCTION BLOCK OPERATIONS
(1) Selection of source oscillation (f(XIN))
The ceramic resonator or RC oscillation can be used for the source oscillation of the MCU. After system is released from reset, the MCU starts operation by the clock output from the on-chip oscillator which is the internal oscillator. When the ceramic resonator is used, execute the CMCK instruction. When the RC oscillation is used, execute the CRCK instruction. The oscillation circuit by the CMCK or CRCK instruction can be selected only at once. The oscillation circuit corresponding to the first executed one of these two instructions is valid. Other oscillation circuit and the on-chip oscillator stop. Execute the CMCK or the CRCK instruction in the initial setting routine of program (executing it in address 0 in page 0 is recommended). Also, when the CMCK or the CRCK instruction is not executed in program, the MCU operates by the on-chip oscillator.
Reset On-chip oscillator operation CMCK instruction CRCK instruction
* Ceramic resonator valid * RC oscillation valid * On-chip oscillator stop * On-chip oscillator stop * Ceramic resonator stop * RC oscillation stop
Fig. 41 Switch to ceramic resonance/RC oscillation
4506
(2) On-chip oscillator operation
When the MCU operates by the on-chip oscillator as the source oscillation (f(XIN)) without using the ceramic resonator or the RC oscillator, connect XIN pin to VSS and leave XOUT pin open (Figure 42). The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that variable frequencies when designing application products.
XIN XOUT
the CMCK instruction * Do not use instruction in program. and CRCK
Fig. 42 Handling of XIN and XOUT when operating on-chip oscillator
4506
(3) Ceramic resonator
When the ceramic resonator is used as the source oscillation (f(XIN)), connect the ceramic resonator and the external circuit to pins XIN and XOUT at the shortest distance. Then, execute the CMCK instruction. A feedback resistor is built in between pins XIN and XOUT (Figure 43).
* Execute the CMCK instruction in program.
XOUT
Note: Externally connect a damping resistor Rd depending on the oscillation frequency. Rd (A feedback resistor is built-in.) Use the resonator manufacturer's recommended value COUT because constants such as capacitance depend on the resonator.
XIN
CIN
(4) RC oscillation
When the RC oscillation is used as the source oscillation (f(XIN)), connect the XIN pin to the external circuit of resistor R and the capacitor C at the shortest distance and leave XOUT pin open. Then, execute the CRCK instruction (Figure 44). The frequency is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits.
Fig. 43 Ceramic resonator external circuit
4506
R C
XIN
XOUT
* ExsercuuctteiotnhenCpRoCgKam. in t irr
Fig. 44 External RC oscillation circuit
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-46
HARDWARE 4506 Group FUNCTION BLOCK OPERATIONS/ROM ORDERING METHOD
(5) External clock
When the external signal clock is used as the source oscillation (f(XIN)), connect the XIN pin to the clock source and leave XOUT pin open. Then, execute the CMCK instruction (Figure 45). Be careful that the maximum value of the oscillation frequency when using the external clock differs from the value when using the ceramic resonator (refer to the recommended operating condition). Also, note that the RAM back-up mode (POF2 instruction) cannot be used when using the external clock.
4506
* ExsercuuctteiotnhenCpMoCKam. in t i r gr
XOUT VDD VSS
XIN
(6) Clock control register MR
Register MR controls system clock. Set the contents of this register through register A with the TMRA instruction. In addition, the TAMR instruction can be used to transfer the contents of register MR to register A. Table 19 Clock control register MR Clock control register MR MR3 System clock selection bits MR2 MR1 MR0 Not used Not used
External oscillation circuit
Fig. 45 External clock input circuit
at reset : 11002 MR3 MR2 0 0 0 1 1 0 1 1 0 1 0 1
at RAM back-up : 11002 System clock
R/W
f(XIN) (high-speed mode) f(XIN)/2 (middle-speed mode) f(XIN)/4 (low-speed mode) f(XIN)/8 (default mode) This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled.
Note : "R" represents read enabled, and "W" represents write enabled.
ROM ORDERING METHOD
Please submit the information described below when ordering Mask ROM. (1) Mask ROM Order Confirmation Form ..................................... 1 (2) Data to be written into mask ROM ............................... EPROM (three sets containing the identical data) (3) Mark Specification Form .......................................................... 1 For the mask ROM confirmation and the mark specifications, refer to the "Renesas Technology Corp." Homepage (http://www.renesas.com/en/rom).
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-47
HARDWARE 4506 Group LIST OF PRECAUTIONS
LIST OF PRECAUTIONS
Noise and latch-up prevention Connect a capacitor on the following condition to prevent noise and latch-up; * connect a bypass capacitor (approx. 0.1 F) between pins VDD and VSS at the shortest distance, * equalize its wiring in width and length, and * use relatively thick wire. In the One Time PROM version, CNVSS pin is also used as VPP pin. Accordingly, when using this pin, connect this pin to VSS through a resistor about 5 k (connect this resistor to CNVSS/ VPP pin as close as possible). Register initial values 1 The initial value of the following registers are undefined after system is released from reset. After system is released from reset, set initial values. * Register Z (2 bits) * Register D (3 bits) * Register E (8 bits) Register initial values 2 The initial value of the following registers are undefined at RAM back-up. After system is returned from RAM back-up, set initial values. * Register Z (2 bits) * Register X (4 bits) * Register Y (4 bits) * Register D (3 bits) * Register E (8 bits) Stack registers (SKS) and stack pointer (SP) Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these operations together. Prescaler Stop the prescaler operation to change its frequency dividing ratio. Timer count source Stop timer 1 or 2 counting to change its count source. Reading the count value Stop timer 1 or 2 counting and then execute the TAB1 or TAB2 instruction to read its data. Writing to the timer Stop timer 1 or 2 counting and then execute the T1AB or T2AB instruction to write its data. Writing to reload register R1 When writing data to reload register R1 while timer 1 is operating, avoid a timing when timer 1 underflows.
10
Timer 1 and timer 2 count start timing and count time when operation starts Count starts from the first rising edge of the count source (2) after timer 1 and timer 2 operations start (1). Time to first underflow (3) is shorter (for up to 1 period of the count source) than time among next underflow (4) by the timing to start the timer and count source operations after count starts. When selecting CNTR input as the count source of timer 2, timer 2 operates synchronizing with the falling edge of CNTR input.
(2) Count Source Count Source (CNTR input) Timer Value 3 2 1 0 3 2 1 0 3 2
Timer Underflow Signal (3) (1) Timer (4)
Fig. 46 Timer count start timing and count time when operation starts (T1, T2)
11 Watchdog timer * The watchdog timer function is valid after system is released from reset. When not using the watchdog timer function, execute the DWDT instruction and the WRST instruction continuously, and clear the WEF flag to "0" to stop the watchdog timer function. * The watchdog timer function is valid after system is returned from the RAM back-up. When not using the watchdog timer function, execute the DWDT instruction and the WRST instruction continuously every system is returned from the RAM back-up, and stop the watchdog timer function.
12 Multifunction * The input/output of D2, D3, P12 and P13 can be used even when C, K, CNTR (input) and INT are selected. * The input of P12 can be used even when CNTR (output) is selected. * The input/output of P20 and P21 can be used even when AIN0 and AIN1 are selected.
13
Program counter Make sure that the PCH does not specify after the last page of the built-in ROM. POF2 instruction When the POF2 instruction is executed continuously after the EPOF instruction, system enters the RAM back-up state. Note that system cannot enter the RAM back-up state when executing only the POF2 instruction. Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction and the POF2 instruction continuously.
14
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-48
HARDWARE 4506 Group LIST OF PRECAUTIONS
15 P13/INT pin Note [1] on bit 3 of register I1 When the input of the INT pin is controlled with the bit 3 of register I1 in software, be careful about the following notes.
Note [3] on bit 2 of register I1 When the interrupt valid waveform of the P13/INT pin is changed with the bit 2 of register I1 in software, be careful about the following notes. * Depending on the input state of the P13/INT pin, the external 0 interrupt request flag (EXF0) may be set when the bit 2 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to "0" (refer to Figure 49) and then, change the bit 2 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to "0" after executing at least one instruction (refer to Figure 49). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 49).
* Depending on the input state of the P13/INT pin, the external 0 interrupt request flag (EXF0) may be set when the bit 3 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to "0" (refer to Figure 47) and then, change the bit 3 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to "0" after executing at least one instruction (refer to Figure 47). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 47).
***
LA 4 TV1A LA 8 TI1A NOP SNZ0 NOP
; (02) ; The SNZ0 instruction is valid ........... ; (12) ; Control of INT pin input is changed ........................................................... ; The SNZ0 instruction is executed (EXF0 flag cleared) ...........................................................
LA 4 TV1A LA 12 TI1A NOP SNZ0 NOP
***
***
Fig. 47 External 0 interrupt program example-1 : these bits are not used here. Note [2] on bit 3 of register I1 When the bit 3 of register I1 is cleared to "0", the RAM back-up mode is selected and the input of INT pin is disabled, be careful about the following notes. * When the key-on wakeup function of port P13 is not used (register K13 = "0"), clear bits 2 and 3 of register I1 before system enters to the RAM back-up mode. (refer to Figure 48). Fig. 49 External 0 interrupt program example-3
16
LA 0 TI1A DI EPOF POF2
; (002) ; Input of INT disabled ........................
Clock control Execute the CMCK or the CRCK instruction in the initial setting routine of program (executing it in address 0 in page 0 is recommended). The oscillation circuit by the CMCK or CRCK instruction can be selected only at once. The oscillation circuit corresponding to the first executed one of these two instruction is valid. Other oscillation circuits and the on-chip oscillator stop. On-chip oscillator The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that variable frequencies when designing application products. Also, the oscillation stabilize wait time after system is released from reset is generated by the on-chip oscillator clock. When considering the oscillation stabilize wait time after system is released from reset, be careful that the variable frequency of the on-chip oscillator clock. External clock When the external signal clock is used as the source oscillation (f(XIN)), note that the RAM back-up mode (POF2 instructions) cannot be used.
***
17
; RAM back-up
: these bits are not used here. Fig. 48 External 0 interrupt program example-2
***
18
***
: these bits are not used here.
; (02) ; The SNZ0 instruction is valid ........... ; (12) ; Interrupt valid waveform is changed ........................................................... ; The SNZ0 instruction is executed (EXF0 flag cleared) ...........................................................
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-49
HARDWARE 4506 Group LIST OF PRECAUTIONS
Notes for the use of A/D conversion 1 Note the following when using the analog input pins also for port P2 function: * Selection of analog input pins Even when P20/AIN0 and P21/AIN1 are set to pins for analog input, they continue to function as port P2 input/output. Accordingly, when any of them are used as I/O port and others are used as analog input pins, make sure to set the outputs of pins that are set for analog input to "1." Also, the port input function of the pin functions as an analog input is undefined. * TALA instruction When the TALA instruction is executed, the low-order 2 bits of register AD is transferred to the high-order 2 bits of register A, simultaneously, the low-order 2 bits of register A is "0."
19
21
Notes for the use of A/D conversion 3 Each analog input pin is equipped with a capacitor which is used to compare the analog voltage. Accordingly, when the analog voltage is input from the circuit with high-impedance and, charge/ discharge noise is generated and the sufficient A/D accuracy may not be obtained. Therefore, reduce the impedance or, connect a capacitor (0.01 F to 1 F) to analog input pins (Figure 51). When the overvoltage applied to the A/D conversion circuit may occur, connect an external circuit in order to keep the voltage within the rated range as shown the Figure 52. In addition, test the application products sufficiently.
Sensor
20
AIN
Notes for the use of A/D conversion 2 Do not change the operating mode (both A/D conversion mode and comparator mode) of A/D converter with the bit 3 of register Q1 while the A/D converter is operating. When the operating mode of A/D converter is changed from the comparator mode to A/D conversion mode with the bit 3 of register Q1, note the following; * Clear the bit 2 of register V2 to "0" (refer to Figure 50) to change the operating mode of the A/D converter from the comparator mode to A/D conversion mode with the bit 3 of register Q1. * The A/D conversion completion flag (ADF) may be set when the operating mode of the A/D converter is changed from the comparator mode to the A/D conversion mode. Accordingly, set a value to the bit 3 of register Q1, and execute the SNZAD instruction to clear the ADF flag.
Apply the voltage withiin the specifications to an analog input pin.
Fig. 51 Analog input external circuit example-1
About 1k
Sensor
AIN
LA 8 TV2A LA 0 TQ1A
***
Fig. 52 Analog input external circuit example-2 ; (02) ; The SNZAD instruction is valid ........ ; (02) ; Operation mode of A/D converter is changed from comparator mode to A/D conversion mode.
22
SNZAD NOP
: this bit is not related to change the operation mode of A/D converter. Fig. 50 A/D conversion interrupt program example
23
Electric Characteristic Differences Between Mask ROM and One Time PROM Version MCU There are differences in electric characteristics, operation margin, noise immunity, and noise radiation between Mask ROM and One Time PROM version MCUs due to the difference in the manufacturing processes. When manufacturing an application system with the One time PROM version and then switching to use of the Mask ROM version, please perform sufficient evaluations for the commercial samples of the Mask ROM version. Note on Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the supply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation.
***
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-50
HARDWARE 4506 Group CONTROL REGISTERS
CONTROL REGISTERS
Interrupt control register V1 V13 V12 V11 V10 Timer 2 interrupt enable bit Timer 1 interrupt enable bit Not used External 0 interrupt enable bit 0 1 0 1 0 1 0 1 at reset : 00002 at RAM back-up : 00002 R/W
Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) (Note 2) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) (Note 2) This bit has no function, but read/write is enabled. Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) (Note 2)
Interrupt control register V2 V23 V22 V21 V20 Not used A/D interrupt enable bit Not used Not used 0 1 0 1 0 1 0 1
at reset : 00002
at RAM back-up : 00002
R/W
This bit has no function, but read/write is enabled. Interrupt disabled (SNZAD instruction is valid) Interrupt enabled (SNZAD instruction is invalid) (Note 2) This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled.
Interrupt control register I1 I13 INT pin input control bit (Note 3) 0 1 0 1 0 1 0 1
at reset : 00002
at RAM back-up : state retained
R/W
INT pin input disabled INT pin input enabled Falling waveform ("L" level of INT pin is recognized with the SNZI0 instruction)/"L" level Rising waveform ("H" level of INT pin is recognized with the SNZI0 instruction)/"H" level One-sided edge detected Both edges detected Disabled Enabled
I12
Interrupt valid waveform for INT pin/ return level selection bit (Note 3)
I11 I10
INT pin edge detection circuit control bit INT pin timer 1 control enable bit
Clock control register MR MR3 System clock selection bits MR2 MR1 MR0 Not used Not used
at reset : 11002 MR3 MR2 0 0 0 1 1 0 1 1 0 1 0 1
at RAM back-up : 11002 System clock
R/W
f(XIN) (high-speed mode) f(XIN)/2 (middle-speed mode) f(XIN)/4 (low-speed mode) f(XIN)/8 (default mode) This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled.
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: These instructions are equivalent to the NOP instruction. 3: When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction when the bit 0 (V10) of register V1 to "0". In this time, set the NOP instruction after the SNZ0 instruction, for the case when a skip is performed with the SNZ0 instruction.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-51
HARDWARE 4506 Group CONTROL REGISTERS
Timer control register W1 W13 W12 W11 W10 Prescaler control bit Prescaler dividing ratio selection bit Timer 1 control bit Timer 1 count start synchronous circuit control bit 0 1 0 1 0 1 0 1
at reset : 00002
at RAM back-up : 00002
R/W
Stop (state initialized) Operating Instruction clock divided by 4 Instruction clock divided by 16 Stop (state retained) Operating Count start synchronous circuit not selected Count start synchronous circuit selected
Timer control register W2 W23 W22 W21 Timer 2 count source selection bits W20 Timer 2 control bit Timer 1 count auto-stop circuit selection bit (Note 2)
at reset : 00002 0 1 0 1 W21 W20 0 0 0 1 1 0 1 1
at RAM back-up : state retained
R/W
Stop (state retained) Operating Count auto-stop circuit not selected Count auto-stop circuit selected Count source Timer 1 underflow signal Prescaler output (ORCLK) CNTR input System clock
Timer control register W6 W63 W62 W61 W60 Not used Not used CNTR output selection bit P12/CNTR function selection bit 0 1 0 1 0 1 0 1
at reset : 00002
at RAM back-up : state retained
R/W
This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. Timer 1 underflow signal divided by 2 output Timer 2 underflow signal divided by 2 output P12(I/O)/CNTR input (Note 3) P12 (input)/CNTR input/output (Note 3)
A/D control register Q1 Q13 Q12 Q11 Analog input pin selection bits Q10 A/D operation mode selection bit Not used
at reset : 00002 0 1 0 1 Q11 Q10 0 0 0 1 1 0 1 1 A/D conversion mode Comparator mode
at RAM back-up : state retained
R/W
This bit has no function, but read/write is enabled. Selected pins AIN0 AIN1 Not available Not available
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: This function is valid only when the timer 1 count start synchronization circuit is selected. 3: CNTR input is valid only when CNTR input is selected as the timer 2 count source.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-52
HARDWARE 4506 Group CONTROL REGISTERS
Key-on wakeup control register K0 K03 K02 K01 K00 Port P03 key-on wakeup control bit Port P02 key-on wakeup control bit Port P01 key-on wakeup control bit Port P00 key-on wakeup control bit 0 1 0 1 0 1 0 1
at reset : 00002
at RAM back-up : state retained
R/W
Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used
Key-on wakeup control register K1 K13 K12 K11 K10 Port P13/INT key-on wakeup control bit Port P12/CNTR key-on wakeup control bit Port P11 key-on wakeup control bit Port P10 key-on wakeup control bit 0 1 0 1 0 1 0 1
at reset : 00002
at RAM back-up : state retained
R/W
P13 key-on wakeup not used/INT pin key-on wakeup used P13 key-on wakeup used/INT pin key-on wakeup not used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used
Key-on wakeup control register K2 K23 K22 K21 K20 Port D3/K key-on wakeup control bit Port D2/C key-on wakeup control bit Port P21/AIN1 key-on wakeup control bit Port P20/AIN0 key-on wakeup control bit 0 1 0 1 0 1 0 1
at reset : 00002
at RAM back-up : state retained
R/W
Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used
Note: "R" represents read enabled, and "W" represents write enabled.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-53
HARDWARE 4506 Group CONTROL REGISTERS
Pull-up control register PU0 PU03 PU02 PU01 PU00 Port P03 pull-up transistor control bit Port P02 pull-up transistor control bit Port P01 pull-up transistor control bit Port P00 pull-up transistor control bit Pull-up control register PU1 PU13 PU12 PU11 PU10 Port P13/INT pull-up transistor control bit Port P12/CNTR pull-up transistor control bit Port P11 pull-up transistor control bit Port P10 pull-up transistor control bit 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
at reset : 00002 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON at reset : 00002 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON
at RAM back-up : state retained
W
at RAM back-up : state retained
W
Pull-up control register PU2 PU23 PU22 PU21 PU20 Port D3/K pull-up transistor control bit Port D2/C pull-up transistor control bit Port P21/AIN1 pull-up transistor control bit Port P20/AIN0 pull-up transistor control bit 0 1 0 1 0 1 0 1
at reset : 00002 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON
at RAM back-up : state retained
W
Notes 1: "R" represents read enabled, and "W" represents write enabled.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-54
HARDWARE 4506 Group INSTRUCTIONS
INSTRUCTIONS
The 4506 Group has the 110 instructions. Each instruction is described as follows; (1) Index list of instruction function (2) Machine instructions (index by alphabet) (3) Machine instructions (index by function) (4) Instruction code table
SYMBOL
The symbols shown below are used in the following list of instruction function and the machine instructions.
Symbol A B DR E Q1 V1 V2 I1 W1 W2 W6 MR K0 K1 K2 PU0 PU1 PU2 X Y Z DP PC PCH PCL SK SP CY R1 R2 T1 T2 T1F T2F Register A (4 bits) Register B (4 bits) Register D (3 bits) Register E (8 bits)
Contents
Symbol WDF1 WEF INTE EXF0 P ADF D P0 P1 P2 C K x y z p n i j A3A2A1A0
Contents Watchdog timer flag Watchdog timer enable flag Interrupt enable flag External 0 interrupt request flag Power down flag A/D conversion completion flag Port D (4 bits) Port P0 (4 bits) Port P1 (4 bits) Port P2 (2 bits) Port C (1 bit) Port K (1 bit) Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal constant Hexadecimal constant Hexadecimal constant Binary notation of hexadecimal variable A (same for others) Direction of data movement Data exchange between a register and memory Decision of state shown before "?" Contents of registers and memories Negate, Flag unchanged after executing instruction RAM address pointed by the data pointer Label indicating address a6 a5 a4 a3 a2 a1 a0 Label indicating address a6 a5 a4 a3 a2 a1 a0 in page p5 p4 p3 p2 p1 p0 Hex. C + Hex. number x (also same for others)
A/D control register Q1 (4 bits) Interrupt control register V1 (4 bits) Interrupt control register V2 (4 bits) Interrupt control register I1 (4 bits) Timer control register W1 (4 bits) Timer control register W2 (4 bits) Timer control register W6 (4 bits) Clock control register MR (4 bits) Key-on wakeup control register K0 (4 bits) Key-on wakeup control register K1 (4 bits) Key-on wakeup control register K2 (4 bits) Pull-up control register PU0 (4 bits) Pull-up control register PU1 (4 bits) Pull-up control register PU2 (4 bits) Register X (4 bits) Register Y (4 bits) Register Z (2 bits) Data pointer (10 bits) (It consists of registers X, Y, and Z) Program counter (14 bits) High-order 7 bits of program counter Low-order 7 bits of program counter Stack register (14 bits 8) Stack pointer (3 bits) Carry flag Timer 1 reload register Timer 2 reload register Timer 1 Timer 2 Timer 1 interrupt request flag Timer 2 interrupt request flag
? () -- M(DP) a p, a C + x
Note : Some instructions of the 4506 Group has the skip function to unexecute the next described instruction. The 4506 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes "1" if the TABP p, RT, or RTS instruction is skipped.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-55
HARDWARE 4506 Group INSTRUCTIONS
INDEX LIST OF INSTRUCTION FUNCTION
GroupMnemonic ing TAB TBA TAY TYA TEAB (A) (B) (B) (A) (A) (Y) (Y) (A) (E7-E4) (B) (E3-E0) (A) TABE (B) (E7-E4) (A) (E3-E0) TDA TAD (DR2-DR0) (A2-A0) (A2-A0) (DR2-DR0) (A3) 0 TAZ (A1, A0) (Z1, Z0) (A3, A2) 0 AM TAX TASP (A) (X) (A2-A0) (SP2-SP0) (A3) 0 LXY x, y (X) x x = 0 to 15 (Y) y y = 0 to 15 66, 88 80, 88 AMC 79, 88 (A) (A) + (M(DP)) + (CY) (CY) Carry 60, 90 (A) (A) + (M(DP)) 60, 90 81, 88 81, 88 76, 88 76, 88 TABP p (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (Note) (PCL) (DR2-DR0, A3-A0) (B) (ROM(PC))7-4 (A) (ROM(PC))3-0 (PC) (SK(SP)) (SP) (SP) - 1 76, 90 Function Page 75, 88 GroupMnemonic ing XAMI j Function (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) + 1 TMA j (M(DP)) (A) (X) (X)EXOR(j) j = 0 to 15 LA n (A) n n = 0 to 15 66, 90 83, 88 Page 87, 88
81, 88 81, 88 86, 88 82, 88
Register to register transfer
Arithmetic operation
RAM to register transfer
An
(A) (A) + n n = 0 to 15 (A) (A) AND (M(DP)) (A) (A) OR (M(DP)) (CY) 1 (CY) 0 (CY) = 0 ? (A) (A) CY A3A2A1A0
60, 90
RAM addresses
AND OR SC
61, 90 68, 90 71, 90 69, 90 74, 90 63, 90 68, 90
LZ z INY DEY TAM j
(Z) z z = 0 to 3 (Y) (Y) + 1 (Y) (Y) - 1 (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15
66, 88 66, 88 63, 88
RC 78, 88 SZC CMA XAM j (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 XAMD j (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) - 1
Note: p is 0 to 15 for M34506M2, p is 0 to 31 for M34506M4/E4.
RAM to register transfer
86, 88 RAR
87, 88
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-56
HARDWARE 4506 Group INSTRUCTIONS
INDEX LIST OF INSTRUCTION FUNCTION (continued)
GroupMnemonic ing SB j Function (Mj(DP)) 1 j = 0 to 3 (Mj(DP)) 0 j = 0 to 3 SZB j (Mj(DP)) = 0 ? j = 0 to 3 (A) = (M(DP)) ? (A) = n ? n = 0 to 15 Ba (PCL) a6-a0 (PCH) p (Note) (PCL) a6-a0 BLA p (PCH) p (Note) (PCL) (DR2-DR0, A3-A0) TI1A BM a (SP) (SP) + 1 (SK(SP)) (PC) (PCH) 2 (PCL) a6-a0 62, 92 TAW1 TW1A 62, 92 TAW2 TW2A TAW6 BMLA p (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (Note) (PCL) (DR2-DR0, A3-A0) RTI (PC) (SK(SP)) (SP) (SP) - 1 RT (PC) (SK(SP)) (SP) (SP) - 1 70, 92 70, 92 62, 92 TW6A (W6) (A) (B) (T17-T14) (A) (T13-T10) T1AB (R17-R14) (B) (T17-T14) (B) (R13-R10) (A) (T13-T10) (A) TAB2 (B) (T27-T24) (A) (T23-T20) T2AB (R27-R24) (B) (T27-T24) (B) (R23-R20) (A) (T23-T20) (A)
Note: p is 0 to 15 for M34506M2, p is 0 to 31 for M34506M4/E4.
Page 70, 90
GroupMnemonic ing DI EI (INTE) 0 (INTE) 1
Function
Page 64, 94 64, 94 72, 94
Bit operation
RB j
69, 90 SNZ0 74, 90 SNZI0 V10 = 0: (EXF0) = 1 ? After skipping, (EXF0) 0 V10 = 1: SNZ0 = NOP I12 = 1 : (INT) = "H" ? I12 = 0 : (INT) = "L" ? TAV1 TV1A TAV2 (A) (V1) (V1) (A) (A) (V2) (V2) (A) (A) (I1) (I1) (A) (A) (W1) (W1) (A) (A) (W2) (W2) (A) (A) (W6) 79, 94 85, 94 79, 94 85, 94 77, 94 82, 94 80, 94 85, 94 80, 94 85, 94 80, 94 86, 94 75, 94 73, 94
Comparison operation
SEAM SEA n
72, 90 71, 90
61, 92 61, 92 TV2A 61, 92 TAI1
Branch operation
BL p, a
Subroutine operation
BML p, a
(SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (Note) (PCL) a6-a0
Timer operation
Interrupt operation
TAB1
74, 94
Return operation
RTS
(PC) (SK(SP)) (SP) (SP) - 1
70, 92
75, 94
75, 94
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-57
HARDWARE 4506 Group INSTRUCTIONS
INDEX LIST OF INSTRUCTION FUNCTION (continued)
Grouping Mnemonic TR1AB Function (R17-R14) (B) (R13-R10) (A) Page 84, 94 GroupMnemonic ing IAK (A0) (K) (A3-A1) 0 73, 94 OKA TK0A 73, 94 TAK0 (K) (A0) (K0) (A) (A) (K0) (K1) (A) (A) (K1) (K2) (A) (A) (K2) (PU0) (A) (PU1) (A) (PU2) (A) In A/D conversion mode (Q13 = 0), (B) (AD9-AD6) (A) (AD5-AD2) RD (D(Y)) 0 (Y) = 0 to 3 SD (D(Y)) 1 (Y) = 0 to 3 SZD (D(Y)) = 0 ? (Y) = 0 to 3 SCP RCP SNZCP (C) 1 (C) 0 (C) = 1 ? 71, 96 69, 96 72, 96 74, 96 71, 96 TALA (A3, A2) (AD1, AD0) (A1, A0) 0 78, 98 69, 96 In comparator mode (Q13 = 1), (B) (AD7-AD4) (A) (AD3-AD0) 67, 96 82, 96 77, 96 82, 96 77, 96 83, 96 78, 96 83, 96 84, 96 84, 96 76, 98 Function Page 65, 96
Timer operation
SNZT1
V12 = 0: (T1F) = 1 ? After skipping, (T1F) 0 V12 = 1: SNZT1 = NOP
SNZT2
V13 = 0: (T2F) = 1 ? After skipping, (T2F) 0 V13 = 1: SNZT2 = NOP
Input/Output operation
TK1A TAK1 TK2A TAK2 TPU0A TPU1A TPU2A
IAP0 OP0A IAP1 OP1A IAP2
(A) (P0) (P0) (A) (A) (P1) (P1) (A) (A1, A0) (P21, P20) (A3, A2) 0
65, 96 67, 96 65, 96 67, 96 65, 96
OP2A CLD
(P21, P20) (A1, A0) (D) 1
68, 96 TABAD 62, 96
Input/Output operation
A/D conversion operation
TADAB
(AD7-AD4) (B) (AD3-AD0) (A)
77, 98
TAQ1 TQ1A ADST
(A) (Q1) (Q1) (A) (ADF) 0 Q13 = 0: A/D conversion starting Q13 = 1: Comparator operation starting
79, 98 84, 98 60, 98
SNZAD
V22 = 0: (ADF) = 1 ? After skipping, (ADF) 0 V22 = 1: SNZAD = NOP
72, 98
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-58
HARDWARE 4506 Group INSTRUCTIONS
INDEX LIST OF INSTRUCTION FUNCTION (continued)
GroupMnemonic ing NOP POF2 EPOF SNZP DWDT Function (PC) (PC) + 1 RAM back-up POF2 instructions valid (P) = 1 ? Stop of watchdog timer function enabled (WDF1) = 1 ? After skipping, (WDF1) 0 Ceramic resonance circuit selected RC oscillation circuit selected (A) (MR) (MR) (A) Page 67, 98 68, 98 64, 98 73, 98 64, 98
Other operation
WRST
86, 98
CMCK
63, 98
CRCK TAMR TMRA
63, 98 78, 98 83, 98
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-59
HARDWARE 4506 Group INSTRUCTIONS
MACHINE INSTRUCTIONS (INDEX BY ALPHABET)
A n (Add n and accumulator)
Instruction code D9 0 0 0 1 1 0 n n n D0 n
2
0
6
n
Number of words
16
Number of cycles 1
Flag CY -
Skip condition Overflow = 0
1
Operation:
(A) (A) + n n = 0 to 15
Grouping: Arithmetic operation Description: Adds the value n in the immediate field to register A, and stores a result in register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. Executes the next instruction when there is overflow as the result of operation.
ADST (A/D conversion STart)
Instruction code D9 1 0 1 0 0 1 1 1 1 D0 1
2
2
9
F
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(ADF) 0 Q13 = 0: A/D conversion starting Q13 = 1: Comparator operation starting (Q13 : bit 3 of A/D control register Q1)
Grouping: A/D conversion operation Description: Clears (0) to A/D conversion completion flag ADF, and the A/D conversion at the A/D conversion mode (Q13 = 0) or the comparator operation at the comparator mode (Q13 = 1) is started.
AM (Add accumulator and Memory)
Instruction code D9 0 0 0 0 0 0 1 0 1 D0 0
2
0
0
A
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (A) + (M(DP))
Grouping: Arithmetic operation Description: Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged.
AMC (Add accumulator, Memory and Carry)
Instruction code D9 0 0 0 0 0 0 1 0 1 D0 1
2
0
0
B
Number of words
16
Number of cycles 1
Flag CY 0/1
Skip condition -
1
Operation:
(A) (A) + (M(DP)) + (CY) (CY) Carry
Grouping: Arithmetic operation Description: Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-60
HARDWARE 4506 Group INSTRUCTIONS
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
AND (logical AND between accumulator and memory)
Instruction code D9 0 0 0 0 0 1 1 0 0 D0 0
2
0
1
8
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (A) AND (M(DP))
Grouping: Arithmetic operation Description: Takes the AND operation between the contents of register A and the contents of M(DP), and stores the result in register A.
B a (Branch to address a)
Instruction code D9 0 1 1 D0 a6 a5 a4 a3 a2 a1 a0
2
1
8 +a
a
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(PCL) a6 to a0
Grouping: Branch operation Description: Branch within a page : Branches to address a in the identical page. Note: Specify the branch address within the page including this instruction.
BL p, a (Branch Long to address a in page p)
Instruction code D9 0 1 Operation: 0 0 1 0 1 1 D0 p4 p3 p2 p1 p0
2
0 2
E +p
p
Number of words
16
Number of cycles 2
Flag CY -
Skip condition -
2
a6 a5 a4 a3 a2 a1 a0 2
a
a 16
(PCH) p (PCL) a6 to a0
Grouping: Branch operation Description: Branch out of a page : Branches to address a in page p. Note: p is 0 to 15 for M34506M2, and p is 0 to 31 for M34506M4/E4.
BLA p (Branch Long to address (D) + (A) in page p)
Instruction code D9 0 1 Operation: 0 0 0 0 0 0 1 0 0 0 0 D0 0
2
0 2
1 p
0
Number of words
16
Number of cycles 2
Flag CY -
Skip condition -
2
p4 0
p3 p2 p1 p0 2
p 16
(PCH) p (PCL) (DR2-DR0, A3-A0)
Grouping: Branch operation Description: Branch out of a page : Branches to address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p. Note: p is 0 to 15 for M34506M2, and p is 0 to 31 for M34506M4/E4.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-61
HARDWARE 4506 Group INSTRUCTIONS
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
BM a (Branch and Mark to address a in page 2)
Instruction code D9 0 1 0 D0 a6 a5 a4 a3 a2 a1 a0
2
1
a
a
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(SP) (SP) + 1 (SK(SP)) (PC) (PCH) 2 (PCL) a6-a0
Grouping: Subroutine call operation Description: Call the subroutine in page 2 : Calls the subroutine at address a in page 2. Note: Subroutine extending from page 2 to another page can also be called with the BM instruction when it starts on page 2. Be careful not to over the stack because the maximum level of subroutine nesting is 8.
BML p, a (Branch and Mark Long to address a in page p)
Instruction code D9 0 1 Operation: 0 0 1 0 1 0 D0 p4 p3 p2 p1 p0
2
0 2
C +p
p
Number of words
16
Number of cycles 2
Flag CY -
Skip condition -
2
a6 a5 a4 a3 a2 a1 a0 2
a
a 16
(SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) a6-a0
Grouping: Subroutine call operation Description: Call the subroutine : Calls the subroutine at address a in page p. Note: p is 0 to 15 for M34506M2, and p is 0 to 31 for M34506M4/E4. Be careful not to over the stack because the maximum level of subroutine nesting is 8.
BMLA p (Branch and Mark Long to address (D) + (A) in page p)
Instruction code D9 0 1 Operation: 0 0 0 0 0 1 1 0 0 0 0 D0 0
2
0 2
3 p
0
Number of words
16
Number of cycles 2
Flag CY -
Skip condition -
2
p4 0
p3 p2 p1 p0 2
p 16
(SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) (DR2-DR0, A3-A0)
Grouping: Subroutine call operation Description: Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p. Note: p is 0 to 15 for M34506M2, and p is 0 to 31 for M34506M4/E4. Be careful not to over the stack because the maximum level of subroutine nesting is 8.
CLD (CLear port D)
Instruction code D9 0 0 0 0 0 1 0 0 0 D0 1
2
0
1
1
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(D) 1
Grouping: Input/Output operation Description: Sets (1) to port D.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-62
HARDWARE 4506 Group INSTRUCTIONS
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
CMA (CoMplement of Accumulator)
Instruction code D9 0 0 0 0 0 1 1 1 0 D0 02 0 1 C 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
Operation:
(A) (A)
Grouping: Arithmetic operation Description: Stores the one's complement for register A's contents in register A.
CMCK (Clock select: ceraMic resonance ClocK)
Instruction code D9 1 0 1 0 0 1 1 0 1 D0 0
2
2
9
A
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
Ceramic resonance circuit selected
Grouping: Other operation Description: Selects the ceramic resonance circuit and stops the on-chip oscillator.
CRCK (Clock select: Rc oscillation ClocK)
Instruction code D9 1 0 1 0 0 1 1 0 1 D0 1
2
2
9
B
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
RC oscillation circuit selected
Grouping: Other operation Description: Selects the RC oscillation circuit and stops the on-chip oscillator.
DEY (DEcrement register Y)
Instruction code D9 0 0 0 0 0 1 0 1 1 D0 1
2
0
1
7
Number of words
16
Number of cycles 1
Flag CY -
Skip condition (Y) = 15
1
Operation:
(Y) (Y) - 1
Grouping: RAM addresses Description: Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-63
HARDWARE 4506 Group INSTRUCTIONS
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
DI (Disable Interrupt)
Instruction code D9 0 0 0 0 0 0 0 1 0 D0 0
2
0
0
4
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(INTE) 0
Grouping: Interrupt control operation Description: Clears (0) to interrupt enable flag INTE, and disables the interrupt. Note: Interrupt is disabled by executing the DI instruction after executing 1 machine cycle.
DWDT (Disable WatchDog Timer)
Instruction code D9 1 0 1 0 0 1 1 1 0 D0 0
2
2
9
C
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
Stop of watchdog timer function enabled
Grouping: Other operation Description: Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction.
EI (Enable Interrupt)
Instruction code D9 0 0 0 0 0 0 0 1 0 D0 1
2
0
0
5
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(INTE) 1
Grouping: Interrupt control operation Description: Sets (1) to interrupt enable flag INTE, and enables the interrupt. Note: Interrupt is enabled by executing the EI instruction after executing 1 machine cycle.
EPOF (Enable POF instruction)
Instruction code D9 0 0 0 1 0 1 1 0 1 D0 1
2
0
5
B
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
POF2 instruction valid
Grouping: Other operation Description: Makes the immediate after POF or POF2 instruction valid by executing the EPOF instruction.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-64
HARDWARE 4506 Group INSTRUCTIONS
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
IAK (Input Accumulator from port K)
Instruction code D9 1 0 0 1 1 0 1 1 1 D0 1
2
2
6
F
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A0) (K) (A3-A1) 0
Grouping: Input/Output operation Description: Transfers the contents of port K to the bit 0 (A0) of register A. Note: After this instruction is executed, "0" is stored to the high-order 3 bits (A3-A1) of register A.
IAP0 (Input Accumulator from port P0)
Instruction code D9 1 0 0 1 1 0 0 0 0 D0 0
2
2
6
0
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (P0)
Grouping: Input/Output operation Description: Transfers the input of port P0 to register A.
IAP1 (Input Accumulator from port P1)
Instruction code D9 1 0 0 1 1 0 0 0 0 D0 1
2
2
6
1
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (P1)
Grouping: Input/Output operation Description: Transfers the input of port P1 to register A.
IAP2 (Input Accumulator from port P2)
Instruction code D9 1 0 0 1 1 0 0 0 1 D0 0
2
2
6
2
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A1, A0) (P21, P20) (A3, A2) 0
Grouping: Input/Output operation Description: Transfers the input of port P2 to the low-order 2 bits (A1, A0) of register A. Note: After this instruction is executed, "0" is stored to the high-order 2 bits (A3, A2) of register A.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-65
HARDWARE 4506 Group INSTRUCTIONS
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
INY (INcrement register Y)
Instruction code D9 0 0 0 0 0 1 0 0 1 D0 1
2
0
1
3 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition (Y) = 0
Operation:
(Y) (Y) + 1
Grouping: RAM addresses Description: Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed.
LA n (Load n in Accumulator)
Instruction code D9 0 0 0 1 1 1 n n n D0 n
2
0
7
n
Number of words
16
Number of cycles 1
Flag CY -
Skip condition Continuous description
1
Operation:
(A) n n = 0 to 15
Grouping: Arithmetic operation Description: Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously are skipped.
LXY x, y (Load register X and Y with x and y)
Instruction code D9 1 1 D0 x3 x2 x1 x0 y3 y2 y1 y0
2
3
x
y
Number of words
16
Number of cycles 1
Flag CY -
Skip condition Continuous description
1
Operation:
(X) x x = 0 to 15 (Y) y y = 0 to 15
Grouping: RAM addresses Description: Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y. When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continuously are skipped.
LZ z (Load register Z with z)
Instruction code D9 0 0 0 1 0 0 1 0 D0 z1 z0
2
0
4
8 +z 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(Z) z z = 0 to 3
Grouping: RAM addresses Description: Loads the value z in the immediate field to register Z.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-66
HARDWARE 4506 Group INSTRUCTIONS
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
NOP (No OPeration)
Instruction code D9 0 0 0 0 0 0 0 0 0 D0 0
2
0
0
0
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(PC) (PC) + 1
Grouping: Other operation Description: No operation; Adds 1 to program counter value, and others remain unchanged.
OKA (Output port K from Accumulator)
Instruction code D9 1 0 0 0 0 1 1 1 1 D0 1
2
2
1
F
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(K) (A0)
Grouping: Input/Output operation Description: Outputs the contents of bit 0 (A0) of register A to port K.
OP0A (Output port P0 from Accumulator)
Instruction code D9 1 0 0 0 1 0 0 0 0 D0 0
2
2
2
0
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(P0) (A)
Grouping: Input/Output operation Description: Outputs the contents of register A to port P0.
OP1A (Output port P1 from Accumulator)
Instruction code D9 1 0 0 0 1 0 0 0 0 D0 1
2
2
2
1
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(P1) (A)
Grouping: Input/Output operation Description: Outputs the contents of register A to port P1.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-67
HARDWARE 4506 Group INSTRUCTIONS
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
OP2A (Output port P2 from Accumulator)
Instruction code D9 1 0 0 0 1 0 0 0 1 D0 0
2
2
2
2
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(P21, P20) (A1, A0)
Grouping: Input/Output operation Description: Outputs the contents of the low-order 2 bits (A1, A0) of register A to port P2.
OR (logical OR between accumulator and memory)
Instruction code D9 0 0 0 0 0 1 1 0 0 D0 12 0 1 9 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
Operation:
(A) (A) OR (M(DP))
Grouping: Arithmetic operation Description: Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result in register A.
POF2 (Power OFf2)
Instruction code D9 0 0 0 0 0 0 1 0 0 D0 0
2
0
0
8
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
RAM back-up
Grouping: Other operation Description: Puts the system in RAM back-up state by executing the POF2 instruction after executing the EPOF instruction. Operations of all functions are stopped. Note: If the EPOF instruction is not executed before executing this instruction, this instruction is equivalent to the NOP instruction.
RAR (Rotate Accumulator Right)
Instruction code D9 0 0 0 0 0 1 1 1 0 D0 1
2
0
1
D
Number of words
16
Number of cycles 1
Flag CY 0/1
Skip condition -
1
Operation:
CY A3A2A1A0
Grouping: Arithmetic operation Description: Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-68
HARDWARE 4506 Group INSTRUCTIONS
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
RB j (Reset Bit)
Instruction code D9 0 0 0 1 0 0 1 1 j D0 j
2
0
4
C +j 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(Mj(DP)) 0 j = 0 to 3
Grouping: Bit operation Description: Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
RC (Reset Carry flag)
Instruction code D9 0 0 0 0 0 0 0 1 1 D0 0
2
0
0
6
Number of words
16
Number of cycles 1
Flag CY 0
Skip condition -
1
Operation:
(CY) 0
Grouping: Arithmetic operation Description: Clears (0) to carry flag CY.
RCP (Reset Port C)
Instruction code D9 1 0 1 0 0 0 1 1 0 D0 0
2
2
8
C
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(C) 0
Grouping: Input/Output operation Description: Clears (0) to port C.
RD (Reset port D specified by register Y)
Instruction code D9 0 0 0 0 0 1 0 1 0 D0 0
2
0
1
4
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(D(Y)) 0 However, (Y) = 0 to 3
Grouping: Input/Output operation Description: Clears (0) to a bit of port D specified by register Y. Note: Set 0 to 3 to register Y because port D is four ports (D0-D3). When values except above are set to register Y, this instruction is equivalent to the NOP instruction.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-69
HARDWARE 4506 Group INSTRUCTIONS
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
RT (ReTurn from subroutine)
Instruction code D9 0 0 0 1 0 0 0 1 0 D0 0
2
0
4
4
Number of words
16
Number of cycles 2
Flag CY -
Skip condition -
1
Operation:
(PC) (SK(SP)) (SP) (SP) - 1
Grouping: Return operation Description: Returns from subroutine to the routine called the subroutine.
RTI (ReTurn from Interrupt)
Instruction code D9 0 0 0 1 0 0 0 1 1 D0 0
2
0
4
6
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(PC) (SK(SP)) (SP) (SP) - 1
Grouping: Return operation Description: Returns from interrupt service routine to main routine. Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous description of the LA/LXY instruction, register A and register B to the states just before interrupt.
RTS (ReTurn from subroutine and Skip)
Instruction code D9 0 0 0 1 0 0 0 1 0 D0 1
2
0
4
5
Number of words
16
Number of cycles 2
Flag CY -
Skip condition Skip at uncondition
1
Operation:
(PC) (SK(SP)) (SP) (SP) - 1
Grouping: Return operation Description: Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition.
SB j (Set Bit)
Instruction code D9 0 0 0 1 0 1 1 1 j D0 j
2
0
5
C +j 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(Mj(DP)) 0 j = 0 to 3
Grouping: Bit operation Description: Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-70
HARDWARE 4506 Group INSTRUCTIONS
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SC (Set Carry flag)
Instruction code D9 0 0 0 0 0 0 0 1 1 D0 1
2
0
0
7
Number of words
16
Number of cycles 1
Flag CY 1
Skip condition -
1
Operation:
(CY) 1
Grouping: Arithmetic operation Description: Sets (1) to carry flag CY.
SCP (Set Port C)
Instruction code D9 1 0 1 0 0 0 1 1 0 D0 1
2
2
8
D
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(C) 1
Grouping: Input/Output operation Description: Sets (1) to port C.
SD (Set port D specified by register Y)
Instruction code D9 0 0 0 0 0 1 0 1 0 D0 1
2
0
1
5
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(D(Y)) 1 (Y) = 0 to 3
Grouping: Input/Output operation Description: Sets (1) to a bit of port D specified by register Y. Note: Set 0 to 3 to register Y because port D is four ports (D0-D3). When values except above are set to register Y, this instruction is equivalent to the NOP instruction.
SEA n (Skip Equal, Accumulator with immediate data n)
Instruction code D9 0 0 Operation: 0 0 0 0 0 1 1 1 0 1 0 n 1 n 0 n D0 1
2
0 0
2 7
5
Number of words
16
Number of cycles 2
Flag CY -
Skip condition (A) = n
2
n2
(A) = n ? n = 0 to 15
n 16 Grouping: Comparison operation Description: Skips the next instruction when the contents of register A is equal to the value n in the immediate field. Executes the next instruction when the contents of register A is not equal to the value n in the immediate field.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-71
HARDWARE 4506 Group INSTRUCTIONS
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SEAM (Skip Equal, Accumulator with Memory)
Instruction code D9 0 0 0 0 1 0 0 1 1 D0 0
2
0
2
6
Number of words
16
Number of cycles 1
Flag CY -
Skip condition (A) = (M(DP))
1
Operation:
(A) = (M(DP)) ?
Grouping: Comparison operation Description: Skips the next instruction when the contents of register A is equal to the contents of M(DP). Executes the next instruction when the contents of register A is not equal to the contents of M(DP).
SNZ0 (Skip if Non Zero condition of external 0 interrupt request flag)
Instruction code D9 0 0 0 0 1 1 1 0 0 D0 0
2
0
3
8
Number of words
16
Number of cycles 1
Flag CY -
Skip condition V10 = 0: (EXF0) = 1
1
Operation:
V10 = 0: (EXF0) = 1 ? After skipping, (EXF0) 0 V10 = 1: SNZ0 = NOP (V10 : bit 0 of the interrupt control register V1)
Grouping: Interrupt operation Description: When V10 = 0 : Skips the next instruction when external 0 interrupt request flag EXF0 is "1." After skipping, clears (0) to the EXF0 flag. When the EXF0 flag is "0," executes the next instruction. When V10 = 1 : This instruction is equivalent to the NOP instruction.
SNZAD (Skip if Non Zero condition of A/D conversion completion flag)
Instruction code D9 1 0 1 0 0 0 0 1 1 D0 1
2
2
8
7
Number of words
16
Number of cycles 1
Flag CY -
Skip condition V22 = 0: (ADF) = 1
1
Operation:
V22 = 0: (ADF) = 1 ? After skipping, (ADF) 0 V22 = 1: SNZAD = NOP (V22 : bit 2 of the interrupt control register V2)
Grouping: A/D conversion operation Description: When V22 = 0 : Skips the next instruction when A/D conversion completion flag ADF is "1." After skipping, clears (0) to the ADF flag. When the ADF flag is "0," executes the next instruction. When V22 = 1 : This instruction is equivalent to the NOP instruction.
SNZCP (Skip if Non Zero condition of Port C)
Instruction code D9 1 0 1 0 0 0 1 0 0 D0 12 2 8 9 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition (C) = 1
Operation:
(C) = 1 ?
Grouping: Input/Output operation Description: Skips the next instruction when the contents of port C is "1." Executes the next instruction when the contents of port C is "0."
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-72
HARDWARE 4506 Group INSTRUCTIONS
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SNZI0 (Skip if Non Zero condition of external 0 Interrupt input pin)
Instruction code D9 0 0 0 0 1 1 1 0 1 D0 02 0 3 A 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition I12 = 0 : (INT) = "L" I12 = 1 : (INT) = "H"
Operation:
I12 = 0 : (INT) = "L" ? I12 = 1 : (INT) = "H" ? (I12 : bit 2 of the interrupt control register I1)
Grouping: Interrupt operation Description: When I12 = 0 : Skips the next instruction when the level of INT pin is "L." Executes the next instruction when the level of INT pin is "H." When I12 = 1 : Skips the next instruction when the level of INT pin is "H." Executes the next instruction when the level of INT pin is "L." Number of words
16
SNZP (Skip if Non Zero condition of Power down flag)
Instruction code D9 0 0 0 0 0 0 0 0 1 D0 1
2
0
0
3
Number of cycles 1
Flag CY -
Skip condition (P) = 1
1
Operation:
(P) = 1 ?
Grouping: Other operation Description: Skips the next instruction when the P flag is "1". After skipping, the P flag remains unchanged. Executes the next instruction when the P flag is "0."
SNZT1 (Skip if Non Zero condition of Timer 1 interrupt request flag)
Instruction code D9 1 0 1 0 0 0 0 0 0 D0 0
2
2
8
0
Number of words
16
Number of cycles 1
Flag CY -
Skip condition V12 = 0: (T1F) = 1
1
Operation:
V12 = 0: (T1F) = 1 ? After skipping, (T1F) 0 V12 = 1: SNZT1 = NOP (V12 = bit 2 of interrupt control register V1)
Grouping: Timer operation Description: When V12 = 0 : Skips the next instruction when timer 1 interrupt request flag T1F is "1." After skipping, clears (0) to the T1F flag. When the T1F flag is "0," executes the next instruction. When V12 = 1 : This instruction is equivalent to the NOP instruction.
SNZT2 (Skip if Non Zero condition of Timer 2 interrupt request flag)
Instruction code D9 1 0 1 0 0 0 0 0 0 D0 1
2
2
8
1
Number of words
16
Number of cycles 1
Flag CY -
Skip condition V13 = 0: (T2F) = 1
1
Operation:
V13 = 0: (T2F) = 1 ? After skipping, (T2F) 0 V13 = 1: SNZT2 = NOP (V13 = bit 3 of interrupt control register V1)
Grouping: Timer operation Description: When V13 = 0 : Skips the next instruction when timer 2 interrupt request flag T2F is "1." After skipping, clears (0) to the T2F flag. When the T2F flag is "0," executes the next instruction. When V13 = 1 : This instruction is equivalent to the NOP instruction.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-73
HARDWARE 4506 Group INSTRUCTIONS
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SZB j (Skip if Zero, Bit)
Instruction code D9 0 0 0 0 1 0 0 0 j D0 j
2
0
2
j
Number of words
16
Number of cycles 1
Flag CY -
Skip condition (Mj(DP)) = 0 j = 0 to 3
1
Operation:
(Mj(DP)) = 0 ? j = 0 to 3
Grouping: Bit operation Description: Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of M(DP) is "0." Executes the next instruction when the contents of bit j of M(DP) is "1."
SZC (Skip if Zero, Carry flag)
Instruction code D9 0 0 0 0 1 0 1 1 1 D0 1
2
0
2
F
Number of words
16
Number of cycles 1
Flag CY -
Skip condition (CY) = 0
1
Operation:
(CY) = 0 ?
Grouping: Arithmetic operation Description: Skips the next instruction when the contents of carry flag CY is "0." After skipping, the CY flag remains unchanged. Executes the next instruction when the contents of the CY flag is "1."
SZD (Skip if Zero, port D specified by register Y)
Instruction code D9 0 0 Operation: 0 0 0 0 0 0 1 1 0 0 0 1 1 0 0 1 D0 0
2
0 0
2 2
4 16 B 16
Number of words 2
Number of cycles 2
Flag CY -
Skip condition (D(Y)) = 0 (Y) = 0 to 3
12
(D(Y)) = 0 ? (Y) = 0 to 3
Grouping: Input/Output operation Description: Skips the next instruction when a bit of port D specified by register Y is "0." Executes the next instruction when the bit is "1." Note: Set 0 to 3 to register Y because port D is four ports (D0-D3). When values except above are set to register Y, this instruction is equivalent to the NOP instruction. D0 Number of words
16
T1AB (Transfer data to timer 1 and register R1 from Accumulator and register B)
Instruction code D9 1 0 0 0 1 1 0 0 0 0
2
2
3
0
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(T17-T14) (B) (R17-R14) (B) (T13-T10) (A) (R13-R10) (A)
Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 reload register R1. Transfers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-74
HARDWARE 4506 Group INSTRUCTIONS
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
T2AB (Transfer data to timer 2 and register R2 from Accumulator and register B)
Instruction code D9 1 0 0 0 1 1 0 0 0 D0 1
2
2
3
1 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(T27-T24) (B) (R27-R24) (B) (T23-T20) (A) (R23-R20) (A)
Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 reload register R2. Transfers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2.
TAB (Transfer data to Accumulator from register B)
Instruction code D9 0 0 0 0 0 1 1 1 1 D0 0
2
0
1
E
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (B)
Grouping: Other operation Description: Transfers the contents of register B to register A.
TAB1 (Transfer data to Accumulator and register B from timer 1)
Instruction code D9 1 0 0 1 1 1 0 0 0 D0 0
2
2
7
0
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(B) (T17-T14) (A) (T13-T10)
Grouping: Timer operation Description: Transfers the high-order 4 bits (T17-T14) of timer 1 to register B. Transfers the low-order 4 bits (T13-T10) of timer 1 to register A.
TAB2 (Transfer data to Accumulator and register B from timer 2)
Instruction code D9 1 0 0 1 1 1 0 0 0 D0 1
2
2
7
1
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(B) (T27-T24) (A) (T23-T20)
Grouping: Timer operation Description: Transfers the high-order 4 bits (T27-T24) of timer 2 to register B. Transfers the low-order 4 bits (T23-T20) of timer 2 to register A.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-75
HARDWARE 4506 Group INSTRUCTIONS
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TABAD (Transfer data to Accumulator and register B from register AD)
Instruction code D9 1 0 0 1 1 1 1 0 0 D0 1
2
2
7
9 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
In A/D conversion mode (Q13 = 0), (B) (AD9-AD6) (A) (AD5-AD2) In comparator mode (Q13 = 1), (B) (AD7-AD4) (A) (AD3-AD0) (Q13 : bit 3 of A/D control register Q1)
Grouping: A/D conversion operation Description: In the A/D conversion mode (Q13 = 0), transfers the high-order 4 bits (AD9-AD6) of register AD to register B, and the middle-order 4 bits (AD5-AD2) of register AD to register A. In the comparator mode (Q13 = 1), transfers the highorder 4 bits (AD7-AD4) of comparator register to register B, and the low-order 4 bits (AD3- AD0) of comparator register to register A. D0 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
TABE (Transfer data to Accumulator and register B from register E)
Instruction code D9 0 0 0 0 1 0 1 0 1 0
2
0
2
A 16
Operation:
(B) (E7-E4) (A) (E3-E0)
Grouping: Register to register transfer Description: Transfers the high-order 4 bits (E7-E4) of register E to register B, and low-order 4 bits of register E to register A.
TABP p (Transfer data to Accumulator and register B from Program memory in page p)
Instruction code D9 0 0 1 0 0 D0 p4 p3 p2 p1 p0
2
0
8 +p
p
Number of words
16
Number of cycles 3
Flag CY -
Skip condition -
1
Operation:
(SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) (DR2-DR0, A3-A0) (B) (ROM(PC))7-4 (A) (ROM(PC))3-0 (PC) (SK(SP)) (SP) (SP) - 1
Grouping: Arithmetic operation Description: Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p. Note: p is 0 to 15 for M34506M2, and p is 0 to 31 for M34506M4/E4. When this instruction is executed, be careful not to over the stack because 1 stage of stack register is used. D0 Number of words
16
TAD (Transfer data to Accumulator from register D)
Instruction code D9 0 0 0 1 0 1 0 0 0 1
2
0
5
1
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A2-A0) (DR2-DR0) (A3) 0
Grouping: Register to register transfer Description: Transfers the contents of register D to the low-order 3 bits (A2-A0) of register A. Note: When this instruction is executed, "0" is stored to the bit 3 (A3) of register A.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-76
HARDWARE 4506 Group INSTRUCTIONS
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TADAB (Transfer data to register AD from Accumulator from register B)
Instruction code D9 1 0 0 0 1 1 1 0 0 D0 1
2
2
3
9
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(AD7-AD4) (B) (AD3-AD0) (A)
Grouping: A/D conversion operation Description: In the A/D conversion mode (Q13 = 0), this instruction is equivalent to the NOP instruction. In the comparator mode (Q13 = 1), transfers the contents of register B to the high-order 4 bits (AD7-AD4) of comparator register, and the contents of register A to the low-order 4 bits (AD3-AD0) of comparator register. (Q13 = bit 3 of A/D control register Q1) D0 Number of words
16
TAI1 (Transfer data to Accumulator from register I1)
Instruction code D9 1 0 0 1 0 1 0 0 1 1
2
2
5
3
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (I1)
Grouping: Interrupt operation Description: Transfers the contents of interrupt control register I1 to register A.
TAK0 (Transfer data to Accumulator from register K0)
Instruction code D9 1 0 0 1 0 1 0 1 1 D0 0
2
2
5
6
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (K0)
Grouping: Input/Output operation Description: Transfers the contents of key-on wakeup control register K0 to register A.
TAK1 (Transfer data to Accumulator from register K1)
Instruction code D9 1 0 0 1 0 1 1 0 0 D0 1
2
2
5
9
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (K1)
Grouping: Input/Output operation Description: Transfers the contents of key-on wakeup control register K1 to register A.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-77
HARDWARE 4506 Group INSTRUCTIONS
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAK2 (Transfer data to Accumulator from register K2)
Instruction code D9 1 0 0 1 0 1 1 0 1 D0 02 2 5 A 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
Operation:
(A) (K2)
Grouping: Input/Output operation Description: Transfers the contents of key-on wakeup control register K2 to register A.
TALA (Transfer data to Accumulator from register LA)
Instruction code D9 1 0 0 1 0 0 1 0 0 D0 1
2
2
4
9 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(A3, A2) (AD1, AD0) (A1, A0) 0
Grouping: A/D conversion operation Description: Transfers the low-order 2 bits (AD1, AD0) of register AD to the high-order 2 bits (A3, A2) of register A. Note: After this instruction is executed, "0" is stored to the low-order 2 bits (A1, A0) of register A.
TAM j (Transfer data to Accumulator from Memory)
Instruction code D9 1 0 1 1 0 0 j j j D0 j
2
2
C
j
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15
Grouping: RAM to register transfer Description: After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
TAMR (Transfer data to Accumulator from register MR)
Instruction code D9 1 0 0 1 0 1 0 0 1 D0 0
2
2
5
2
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (MR)
Grouping: Other operation Description: Transfers the contents of clock control register MR to register A.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-78
HARDWARE 4506 Group INSTRUCTIONS
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAQ1 (Transfer data to Accumulator from register Q1)
Instruction code D9 1 0 0 1 0 0 0 1 0 D0 0
2
2
4
4
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (Q1)
Grouping: A/D conversion operation Description: Transfers the contents of A/D control register Q1 to register A.
TASP (Transfer data to Accumulator from Stack Pointer)
Instruction code D9 0 0 0 1 0 1 0 0 0 D0 0
2
0
5
0
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A2-A0) (SP2-SP0) (A3) 0
Grouping: Register to register transfer Description: Transfers the contents of stack pointer (SP) to the low-order 3 bits (A2-A0) of register A. Note: After this instruction is executed, "0" is stored to the bit 3 (A3) of register A.
TAV1 (Transfer data to Accumulator from register V1)
Instruction code D9 0 0 0 1 0 1 0 1 0 D0 0
2
0
5
4
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (V1)
Grouping: Interrupt operation Description: Transfers the contents of interrupt control register V1 to register A.
TAV2 (Transfer data to Accumulator from register V2)
Instruction code D9 0 0 0 1 0 1 0 1 0 D0 1
2
0
5
5
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (V2)
Grouping: Interrupt operation Description: Transfers the contents of interrupt control register V2 to register A.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-79
HARDWARE 4506 Group INSTRUCTIONS
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAW1 (Transfer data to Accumulator from register W1)
Instruction code D9 1 0 0 1 0 0 1 0 1 D0 1
2
2
4
B 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(A) (W1)
Grouping: Timer operation Description: Transfers the contents of timer control register W1 to register A.
TAW2 (Transfer data to Accumulator from register W2)
Instruction code D9 1 0 0 1 0 0 1 1 0 D0 0
2
2
4
C
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (W2)
Grouping: Timer operation Description: Transfers the contents of timer control register W2 to register A.
TAW6 (Transfer data to Accumulator from register W6)
Instruction code D9 1 0 0 1 0 1 0 0 0 D0 0
2
2
5
0
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (W6)
Grouping: Timer operation Description: Transfers the contents of timer control register W6 to register A.
TAX (Transfer data to Accumulator from register X)
Instruction code D9 0 0 0 1 0 1 0 0 1 D0 0
2
0
5
2
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (X)
Grouping: Register to register transfer Description: Transfers the contents of register X to register A.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-80
HARDWARE 4506 Group INSTRUCTIONS
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAY (Transfer data to Accumulator from register Y)
Instruction code D9 0 0 0 0 0 1 1 1 1 D0 12 0 1 F 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
Operation:
(A) (Y)
Grouping: Register to register transfer Description: Transfers the contents of register Y to register A.
TAZ (Transfer data to Accumulator from register Z)
Instruction code D9 0 0 0 1 0 1 0 0 1 D0 12 0 5 3 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
Operation:
(A1, A0) (Z1, Z0) (A3, A2) 0
Grouping: Register to register transfer Description: Transfers the contents of register Z to the low-order 2 bits (A1, A0) of register A. Note: After this instruction is executed, "0" is stored to the high-order 2 bits (A3, A2) of register A.
TBA (Transfer data to register B from Accumulator)
Instruction code D9 0 0 0 0 0 0 1 1 1 D0 0
2
0
0
E
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(B) (A)
Grouping: Register to register transfer Description: Transfers the contents of register A to register B.
TDA (Transfer data to register D from Accumulator)
Instruction code D9 0 0 0 0 1 0 1 0 0 D0 1
2
0
2
9
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(DR2-DR0) (A2-A0)
Grouping: Register to register transfer Description: Transfers the contents of the low-order 3 bits (A2-A0) of register A to register D.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-81
HARDWARE 4506 Group INSTRUCTIONS
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TEAB (Transfer data to register E from Accumulator and register B)
Instruction code D9 0 0 0 0 0 1 1 0 1 D0 0
2
0
1
A 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(E7-E4) (B) (E3-E0) (A)
Grouping: Register to register transfer Description: Transfers the contents of register B to the high-order 4 bits (E3-E0) of register E, and the contents of register A to the low-order 4 bits (E3-E0) of register E.
TI1A (Transfer data to register I1 from Accumulator)
Instruction code D9 1 0 0 0 0 1 0 1 1 D0 1
2
2
1
7 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(I1) (A)
Grouping: Interrupt operation Description: Transfers the contents of register A to interrupt control register I1.
TK0A (Transfer data to register K0 from Accumulator)
Instruction code D9 1 0 0 0 0 1 1 0 1 D0 1
2
2
1
B
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(K0) (A)
Grouping: Input/Output operation Description: Transfers the contents of register A to keyon wakeup control register K0.
TK1A (Transfer data to register K1 from Accumulator)
Instruction code D9 1 0 0 0 0 1 0 1 0 D0 0
2
2
1
4
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(K1) (A)
Grouping: Input/Output operation Description: Transfers the contents of register A to keyon wakeup control register K1.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-82
HARDWARE 4506 Group INSTRUCTIONS
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TK2A (Transfer data to register K2 from Accumulator)
Instruction code D9 1 0 0 0 0 1 0 1 0 D0 1
2
2
1
5
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(K2) (A)
Grouping: Input/Output operation Description: Transfers the contents of register A to keyon wakeup control register K2.
TMA j (Transfer data to Memory from Accumulator)
Instruction code D9 1 0 1 0 1 1 j j j D0 j
2
2
B
j
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(M(DP)) (A) (X) (X)EXOR(j) j = 0 to 15
Grouping: RAM to register transfer Description: After transferring the contents of register A to M(DP), an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
TMRA (Transfer data to register MR from Accumulator)
Instruction code D9 1 0 0 0 0 1 0 1 1 D0 0
2
2
1
6
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(MR) (A)
Grouping: Other operation Description: Transfers the contents of register A to clock control register MR.
TPU0A (Transfer data to register PU0 from Accumulator)
Instruction code D9 1 0 0 0 1 0 1 1 0 D0 1
2
2
2
D
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(PU0) (A)
Grouping: Input/Output operation Description: Transfers the contents of register A to pullup control register PU0.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-83
HARDWARE 4506 Group INSTRUCTIONS
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TPU1A (Transfer data to register PU1 from Accumulator)
Instruction code D9 1 0 0 0 1 0 1 1 1 D0 0
2
2
2
E
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(PU1) (A)
Grouping: Input/Output operation Description: Transfers the contents of register A to pullup control register PU1.
TPU2A (Transfer data to register PU2 from Accumulator)
Instruction code D9 1 0 0 0 1 0 1 1 1 D0 1
2
2
2
F
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(PU2) (A)
Grouping: Input/Output operation Description: Transfers the contents of register A to pullup control register PU2.
TQ1A (Transfer data to register Q1 from Accumulator)
Instruction code D9 1 0 0 0 0 0 0 1 0 D0 0
2
2
0
4
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(Q1) (A)
Grouping: A/D conversion operation Description: Transfers the contents of register A to A/D control register Q1.
TR1AB (Transfer data to register R1 from Accumulator and register B)
Instruction code D9 1 0 0 0 1 1 1 1 1 D0 1
2
2
3
F
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(R17-R14) (B) (R13-R10) (A)
Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits (R17-R14) of reload register R1, and the contents of register A to the low-order 4 bits (R13-R10) of reload register R1.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-84
HARDWARE 4506 Group INSTRUCTIONS
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TV1A (Transfer data to register V1 from Accumulator)
Instruction code D9 0 0 0 0 1 1 1 1 1 D0 12 0 3 F 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
Operation:
(V1) (A)
Grouping: Interrupt operation Description: Transfers the contents of register A to interrupt control register V1.
TV2A (Transfer data to register V2 from Accumulator)
Instruction code D9 0 0 0 0 1 1 1 1 1 D0 02 0 3 E 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
Operation:
(V2) (A)
Grouping: Interrupt operation Description: Transfers the contents of register A to interrupt control register V2.
TW1A (Transfer data to register W1 from Accumulator)
Instruction code D9 1 0 0 0 0 0 1 1 1 D0 0
2
2
0
E
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(W1) (A)
Grouping: Timer operation Description: Transfers the contents of register A to timer control register W1.
TW2A (Transfer data to register W2 from Accumulator)
Instruction code D9 1 0 0 0 0 0 1 1 1 D0 1
2
2
0
F
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(W2) (A)
Grouping: Timer operation Description: Transfers the contents of register A to timer control register W2.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-85
HARDWARE 4506 Group INSTRUCTIONS
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TW6A (Transfer data to register W6 from Accumulator)
Instruction code D9 1 0 0 0 0 1 0 0 1 D0 12 2 1 3 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
Operation:
(W6) (A)
Grouping: Timer operation Description: Transfers the contents of register A to timer control register W6.
TYA (Transfer data to register Y from Accumulator)
Instruction code D9 0 0 0 0 0 0 1 1 0 D0 0
2
0
0
C
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(Y) (A)
Grouping: Register to register transfer Description: Transfers the contents of register A to register Y.
WRST (Watchdog timer ReSeT)
Instruction code D9 1 0 1 0 1 0 0 0 0 D0 0
2
2
A
0
Number of words
16
Number of cycles 1
Flag CY -
Skip condition (WDF1) = 1
1
Operation:
(WDF1) = 1 ? After skipping, (WDF1) 0
Grouping: Other operation Description: Skips the next instruction when watchdog timer flag WDF1 is "1." After skipping, clears (0) to the WDF1 flag. When the WDF1 flag is "0," executes the next instruction. Also, stops the watchdog timer function when executing the WRST instruction immediately after the DWDT instruction.
XAM j (eXchange Accumulator and Memory data)
Instruction code D9 1 0 1 1 0 1 j j j D0 j
2
2
D
j
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15
Grouping: RAM to register transfer Description: After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-86
HARDWARE 4506 Group INSTRUCTIONS
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
XAMD j (eXchange Accumulator and Memory data and Decrement register Y and skip)
Instruction code D9 1 0 1 1 1 1 j j j D0 j
2
2
F
j
Number of words
16
Number of cycles 1
Flag CY -
Skip condition (Y) = 15
1
Operation:
(A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) - 1
Grouping: RAM to register transfer Description: After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. D0 Number of words
16
XAMI j (eXchange Accumulator and Memory data and Increment register Y and skip)
Instruction code D9 1 0 1 1 1 0 j j j j
2
2
E
j
Number of cycles 1
Flag CY -
Skip condition (Y) = 0
1
Operation:
(A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) + 1
Grouping: RAM to register transfer Description: After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. when the contents of register Y is not 0, the next instruction is executed. D0
2 16
Instruction code
D9
Number of words
Number of cycles
Flag CY
Skip condition
Instruction code
D9
D0
2 16
Number of words
Number of cycles
Flag CY
Skip condition
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-87
HARDWARE 4506 Group INSTRUCTIONS
MACHINE INSTRUCTIONS (INDEX BY TYPES)
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TAB TBA TAY TYA 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 1 1 0 0
01E 00E 01F 00C 01A 02A 029 051 053 052 050 3xy
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1
(A) (B) (B) (A) (A) (Y) (Y) (A) (E7-E4) (B) (E3-E0) (A) (B) (E7-E4) (A) (E3-E0) (DR2-DR0) (A2-A0) (A2-A0) (DR2-DR0) (A3) 0 (A1, A0) (Z1, Z0) (A3, A2) 0 (A) (X) (A2-A0) (SP2-SP0) (A3) 0 (X) x x = 0 to 15 (Y) y y = 0 to 15 (Z) z z = 0 to 3 (Y) (Y) + 1 (Y) (Y) - 1
Register to register transfer
TEAB TABE TDA TAD TAZ TAX TASP LXY x, y
x3 x2 x1 x0 y3 y2 y1 y0
RAM addresses
LZ z INY DEY
0 0 0
0 0 0
0 0 0
1 0 0
0 0 0
0 1 1
1 0 0
0 0 1
z1 z0 1 1 1 1
048 +z 013 017
1 1 1
1 1 1
TAM j
1
0
1
1
0
0
j
j
j
j
2Cj
1
1
(A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) - 1 (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) + 1 (M(DP)) (A) (X) (X)EXOR(j) j = 0 to 15
RAM to register transfer
XAM j
1
0
1
1
0
1
j
j
j
j
2Dj
1
1
XAMD j
1
0
1
1
1
1
j
j
j
j
2Fj
1
1
XAMI j
1
0
1
1
1
0
j
j
j
j
2Ej
1
1
TMA j
1
0
1
0
1
1
j
j
j
j
2Bj
1
1
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-88
HARDWARE 4506 Group INSTRUCTIONS
Skip condition
Carry flag CY
Datailed description
- - - - - - - - - - - Continuous description - (Y) = 0 (Y) = 15
- - - - - - - - - - - -
Transfers the contents of register B to register A. Transfers the contents of register A to register B. Transfers the contents of register Y to register A. Transfers the contents of register A to register Y. Transfers the contents of register B to the high-order 4 bits (E3-E0) of register E, and the contents of register A to the low-order 4 bits (E3-E0) of register E. Transfers the high-order 4 bits (E7-E4) of register E to register B, and low-order 4 bits of register E to register A. Transfers the contents of the low-order 3 bits (A2-A0) of register A to register D. Transfers the contents of register D to the low-order 3 bits (A2-A0) of register A. Transfers the contents of register Z to the low-order 2 bits (A1, A0) of register A. Transfers the contents of register X to register A. Transfers the contents of stack pointer (SP) to the low-order 3 bits (A2-A0) of register A. Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y. When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continuously are skipped. Loads the value z in the immediate field to register Z. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. when the contents of register Y is not 0, the next instruction is executed. After transferring the contents of register A to M(DP), an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
- - -
-
-
-
-
(Y) = 15
-
(Y) = 0
-
-
-
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-89
HARDWARE 4506 Group INSTRUCTIONS
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LA n 0 0 0 1 1 1 n n n n
07n
1
1
(A) n n = 0 to 15 (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (Note) (PCL) (DR2-DR0, A3-A0) (B) (ROM(PC))7-4 (A) (ROM(PC))3-0 (PC) (SK(SP)) (SP) (SP) - 1 (A) (A) + (M(DP)) (A) (A) + (M(DP)) +(CY) (CY) Carry (A) (A) + n n = 0 to 15
TABP p
0
0
1
0
0
p4 p3 p2 p1 p0
08p +p
1
3
AM
0 0 0
0 0 0
0 0 0
0 0 1
0 0 1
0 0 0
1 1 n
0 0 n
1 1 n
0 1 n
00A 00B 06n
1 1 1
1 1 1
Arithmetic operation
AMC An
AND OR SC RC SZC CMA RAR SB j
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1 1 0
0 0 0 0 1 0 0 0 0 1
1 1 0 0 0 1 1 1 0 0
1 1 0 0 1 1 1 1 1 0
0 0 1 1 1 1 1 1 1 0
0 0 1 1 1 0 0 j j j
0 1 1 0 1 0 1 j j j
018 019 007 006 02F 01C 01D 05C +j 04C +j 02j
1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1
(A) (A) AND (M(DP)) (A) (A) OR (M(DP)) (CY) 1 (CY) 0 (CY) = 0 ? (A) (A) CY A3A2A1A0 (Mj(DP)) 1 j = 0 to 3 (Mj(DP)) 0 j = 0 to 3 (Mj(DP)) = 0 ? j = 0 to 3 (A) = (M(DP)) ?
Bit operation
RB j SZB j
SEAM
0
0
0
0
1
0
0
1
1
0
026
1
1
Comparison
operation
SEA n
0 0
0 0
0 0
0 1
1 1
0 1
0 n
1 n
0 n
1 n
025 07n
2
2
(A) = n ? n = 0 to 15
Note : p is 0 to 15 for M34506M2, p is 0 to 31 for M34506M4/E4.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-90
HARDWARE 4506 Group INSTRUCTIONS
Skip condition
Carry flag CY
Datailed description
Continuous description -
-
Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously are skipped. Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p. When this instruction is executed, be careful not to over the stack because 1 stage of stack register is used.
-
- - Overflow = 0
-
Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged.
0/1 Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY. - Adds the value n in the immediate field to register A, and stores a result in register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. Executes the next instruction when there is overflow as the result of operation. Takes the AND operation between the contents of register A and the contents of M(DP), and stores the result in register A. Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result in register A. Sets (1) to carry flag CY. Clears (0) to carry flag CY. Skips the next instruction when the contents of carry flag CY is "0." Stores the one's complement for register A's contents in register A.
- - - - (CY) = 0 - - - - (Mj(DP)) = 0 j = 0 to 3 (A) = (M(DP))
- - 1 0 - -
0/1 Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right. - - - Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of M(DP) is "0." Executes the next instruction when the contents of bit j of M(DP) is "1." Skips the next instruction when the contents of register A is equal to the contents of M(DP). Executes the next instruction when the contents of register A is not equal to the contents of M(DP). Skips the next instruction when the contents of register A is equal to the value n in the immediate field. Executes the next instruction when the contents of register A is not equal to the value n in the immediate field.
-
(A) = n
-
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-91
HARDWARE 4506 Group INSTRUCTIONS
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Ba BL p, a 0 0 1 BLA p 0 1 BM a 0 1 0 0 0 0 1 1 1 0 0 0 0 a6 a5 a4 a3 a2 a1 a0 1 1 p4 p3 p2 p1 p0
18a +a 0Ep +p 2aa 010 2pp 1aa
1 2
1 2
(PCL) a6-a0 (PCH) p (Note) (PCL) a6-a0
Branch operation
a6 a5 a4 a3 a2 a1 a0 0 0 1 0 0 0 0 0
2
2
(PCH) p (Note) (PCL) (DR2-DR0, A3-A0)
p4 0
p3 p2 p1 p0
a6 a5 a4 a3 a2 a1 a0
1
1
Subroutine operation
(SP) (SP) + 1 (SK(SP)) (PC) (PCH) 2 (PCL) a6-a0 (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (Note) (PCL) a6-a0 (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (Note) (PCL) (DR2-DR0,A3-A0) (PC) (SK(SP)) (SP) (SP) - 1 (PC) (SK(SP)) (SP) (SP) - 1 (PC) (SK(SP)) (SP) (SP) - 1
BML p, a
0 1
0 0 0 0
1 0 0 0
1
0
p4 p3 p2 p1 p0
0Cp +p 2aa 030 2pp
2
2
a6 a5 a4 a3 a2 a1 a0 0 1 1 0 0 0 0 0
BMLA p
0 1
2
2
p4 0
p3 p2 p1 p0
RTI
0
0
0
1
0
0
0
1
1
0
046
1
1
Return operation
RT
0
0
0
1
0
0
0
1
0
0
044
1
2
RTS
0
0
0
1
0
0
0
1
0
1
045
1
2
Note : p is 0 to 15 for M34506M2, p is 0 to 31 for M34506M4/E4.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-92
HARDWARE 4506 Group INSTRUCTIONS
Skip condition
Carry flag CY
Datailed description
- -
- -
Branch within a page : Branches to address a in the identical page. Branch out of a page : Branches to address a in page p.
-
-
Branch out of a page : Branches to address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p.
-
-
Call the subroutine in page 2 : Calls the subroutine at address a in page 2.
-
-
Call the subroutine : Calls the subroutine at address a in page p.
-
-
Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p.
-
-
Returns from interrupt service routine to main routine. Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous description of the LA/LXY instruction, register A and register B to the states just before interrupt. Returns from subroutine to the routine called the subroutine.
-
-
Skip at uncondition
-
Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-93
HARDWARE 4506 Group INSTRUCTIONS
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DI EI SNZ0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 1 1 0 0 0 0 0 1 0
004 005 038
1 1 1
1 1 1
(INTE) 0 (INTE) 1 V10 = 0: (EXF0) = 1 ? After skipping, (EXF0) 0 V10 = 1: SNZ0 = NOP I12 = 0 : (INT) = "L" ? I12 = 1 : (INT) = "H" ?
Interrupt operation
SNZI0
0
0
0
0
1
1
1
0
1
0
03A
1
1
TAV1 TV1A TAV2 TV2A TAI1 TI1A TAW1 TW1A TAW2 TW2A TAW6 TW6A TAB1 T1AB
0 0 0 0 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 1 0 1 0 1 0 1 0 1 0 1 0
0 1 0 1 0 0 0 0 0 0 0 0 1 1
1 1 1 1 1 1 0 0 0 0 1 1 1 1
0 1 0 1 0 0 1 1 1 1 0 0 0 0
1 1 1 1 0 1 0 1 1 1 0 0 0 0
0 1 0 1 1 1 1 1 0 1 0 1 0 0
0 1 1 0 1 1 1 0 0 1 0 1 0 0
054 03F 055 03E 253 217 24B 20E 24C 20F 250 213 270 230
1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1
(A) (V1) (V1) (A) (A) (V2) (V2) (A) (A) (I1) (I1) (A) (A) (W1) (W1) (A) (A) (W2) (W2) (A) (A) (W6) (W6) (A) (B) (T17-T14) (A) (T13-T10) (T17-T14) (B) (R17-R14) (B) (T13-T10) (A) (R13-R10) (A) (B) (T27-T24) (A) (T23-T20) (T27-T24) (B) (R27-R24) (B) (T23-T20) (A) (R23-R20) (A) (R17-R14) (B) (R13-R10) (A) V12 = 0: (T1F) = 1 ? After skipping, (T1F) 0 V12 = 1: SNZT1 = NOP V13 = 0: (T2F) = 1 ? After skipping, (T2F) 0 V13 = 1: SNZT2 = NOP
Timer operation
TAB2 T2AB
1 1
0 0
0 0
1 0
1 1
1 1
0 0
0 0
0 0
1 1
271 231
1 1
1 1
TR1AB SNZT1
1 1
0 0
0 1
0 0
1 0
1 0
1 0
1 0
1 0
1 0
23F 280
1 1
1 1
SNZT2
1
0
1
0
0
0
0
0
0
1
281
1
1
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-94
HARDWARE 4506 Group INSTRUCTIONS
Skip condition
Carry flag CY
Datailed description
- - V10 = 0: (EXF0) = 1
- - -
Clears (0) to interrupt enable flag INTE, and disables the interrupt. Sets (1) to interrupt enable flag INTE, and enables the interrupt. When V10 = 0 : Skips the next instruction when external 0 interrupt request flag EXF0 is "1." After skipping, clears (0) to the EXF0 flag. When the EXF0 flag is "0," executes the next instruction. When V10 = 1 : This instruction is equivalent to the NOP instruction. (V10: bit 0 of interrupt control register V1) When I12 = 0 : Skips the next instruction when the level of INT pin is "L." Executes the next instruction when the level of INT pin is "H." When I12 = 1 : Skips the next instruction when the level of INT pin is "H." Executes the next instruction when the level of INT pin is "L." (I12: bit 2 of interrupt control register I1)
(INT) = "L" However, I12 = 0 (INT) = "H" However, I12 = 1 - - - - - - - - - - - - - -
-
- - - - - - - - - - - - - -
Transfers the contents of interrupt control register V1 to register A. Transfers the contents of register A to interrupt control register V1. Transfers the contents of interrupt control register V2 to register A. Transfers the contents of register A to interrupt control register V2. Transfers the contents of interrupt control register I1 to register A. Transfers the contents of register A to interrupt control register I1. Transfers the contents of timer control register W1 to register A. Transfers the contents of register A to timer control register W1. Transfers the contents of timer control register W2 to register A. Transfers the contents of register A to timer control register W2. Transfers the contents of timer control register W6 to register A. Transfers the contents of register A to timer control register W6. Transfers the high-order 4 bits (T17-T14) of timer 1 to register B. Transfers the low-order 4 bits (T13-T10) of timer 1 to register A. Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 reload register R1. Transfers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1.
- -
- -
Transfers the high-order 4 bits (T27-T24) of timer 2 to register B. Transfers the low-order 4 bits (T23-T20) of timer 2 to register A. Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 reload register R2. Transfers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2.
- V12 = 0: (T1F) = 1
- -
Transfers the contents of register B to the high-order 4 bits (R17-R14) of reload register R1, and the contents of register A to the low-order 4 bits (R13-R10) of reload register R1. When V12 = 0 : Skips the next instruction when timer 1 interrupt request flag T1F is "1." After skipping, clears (0) to the T1F flag. When the T1F flag is "0," executes the next instruction. When V12 = 1 : This instruction is equivalent to the NOP instruction. (V12: bit 2 of interrupt control register V1) When V13 = 0 : Skips the next instruction when timer 1 interrupt request flag T2F is "1." After skipping, clears (0) to the T2F flag. When the T2F flag is "0," executes the next instruction. When V13 = 1 : This instruction is equivalent to the NOP instruction. (V13: bit 3 of interrupt control register V1)
V13 = 0: (T2F) =1
-
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-95
HARDWARE 4506 Group INSTRUCTIONS
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 IAP0 OP0A IAP1 OP1A IAP2 OP2A CLD RD 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 1 0
260 220 261 221 262 222 011 014
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
(A) (P0) (P0) (A) (A) (P1) (P1) (A) (A1, A0) (P21, P20) (A3, A2) 0 (P21, P20) (A1, A0) (D) 1 (D(Y)) 0 (Y) = 0 to 3 (D(Y)) 1 (Y) = 0 to 3 (D(Y)) = 0 ? (Y) = 0 to 3
SD
0
0
0
0
0
1
0
1
0
1
015
1
1
SZD
0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 1 0 0 1 0 1 0 1 0 0 0
1 1 0 0 0 1 0 0 0 0 0 0 0 1 1 1
0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0
0 1 1 1 1 1 1 1 0 0 1 0 1 1 1 1
1 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1
0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1
0 1 1 0 1 1 1 1 0 0 1 1 0 1 0 1
024 02B 28D 28C 289 26F 21F 21B 256 214 259 215 25A 22D 22E 22F
2
2
Input/Output operation
SCP RCP SNZCP IAK OKA TK0A TAK0 TK1A TAK1 TK2A TAK2 TPU0A TPU1A TPU2A
1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1
(C) 1 (C) 0 (C) = 1? (A0) (K) (A3-A1) 0 (K) (A0) (K0) (A) (A) (K0) (K1) (A) (A) (K1) (K2) (A) (A) (K2) (PU0) (A) (PU1) (A) (PU2) (A)
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-96
HARDWARE 4506 Group INSTRUCTIONS
Skip condition
Carry flag CY
Datailed description
- - - - - - - -
- - - - - - - -
Transfers the input of port P0 to register A. Outputs the contents of register A to port P0. Transfers the input of port P1 to register A. Outputs the contents of register A to port P1. Transfers the input of port P2 to the low-order 2 bits (A1, A0) of register A. Outputs the contents of the low-order 2 bits (A1, A0) of register A to port P2. Sets (1) to port D. Clears (0) to a bit of port D specified by register Y.
-
-
Sets (1) to a bit of port D specified by register Y.
(D(Y)) = 0 ? (Y) = 0 to 3
-
Skips the next instruction when a bit of port D specified by register Y is "0." Executes the next instruction when a bit of port D specified by register Y is "1."
- - (C) = 1 - - - - - - - - - - -
- - - - - - - - - - - - - -
Sets (1) to port C. Clears (0) to port C. Skips the next instruction when the contents of port C is "1." Executes the next instruction when the contents of port C is "0." Transfers the contents of port K to the bit 0 (A0) of register A. Outputs the contents of bit 0 (A0) of register A to port K. Transfers the contents of register A to key-on wakeup control register K0. Transfers the contents of key-on wakeup control register K0 to register A. Transfers the contents of register A to key-on wakeup control register K1. Transfers the contents of key-on wakeup control register K1 to register A. Transfers the contents of register A to key-on wakeup control register K2. Transfers the contents of key-on wakeup control register K2 to register A. Transfers the contents of register A to pull-up control register PU0. Transfers the contents of register A to pull-up control register PU1. Transfers the contents of register A to pull-up control register PU2.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-97
HARDWARE 4506 Group INSTRUCTIONS
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TABAD 1 0 0 1 1 1 1 0 0 1
279
1
1
In A/D conversion mode (Q13 = 0), (B) (AD9-AD6) (A) (AD5-AD2) In comparator mode (Q13 = 1), (B) (AD7-AD4) (A) (AD3-AD0) (A3, A2) (AD1, AD0) (A1, A0) 0 (AD7-AD4) (B) (AD3-AD0) (A)
A/D conversion operation
TALA TADAB
1 1
0 0
0 0
1 0
0 1
0 1
1 1
0 0
0 0
1 1
249 239
1 1
1 1
TAQ1 TQ1A ADST
1 1 1
0 0 0
0 0 1
1 0 0
0 0 0
0 0 1
0 0 1
1 1 1
0 0 1
0 0 1
244 204 29F
1 1 1
1 1 1
(A) (Q1) (Q1) (A) (ADF) 0 Q13 = 0: A/D conversion starting Q13 = 1: Comparator operation starting V22 = 0: (ADF) = 1 ? After skipping, (ADF) 0 V22 = 1: SNZAD = NOP (PC) (PC) + 1 RAM back-up POF2 instruction valid (P) = 1 ?
SNZAD
1
0
1
0
0
0
0
1
1
1
287
1
1
NOP POF2 EPOF SNZP
0 0 0 0
0 0 0 0
0 0 0 0
0 0 1 0
0 0 0 0
0 0 1 0
0 1 1 0
0 0 0 0
0 0 1 1
0 0 1 1
000 008 05B 003
1 1 1 1
1 1 1 1
Other operation
DWDT WRST
1 1
0 0
1 1
0 0
0 1
1 0
1 0
1 0
0 0
0 0
29C 2A0
1 1
1 1
Stop of watchdog timer function enabled (WDF1) = 1 ?, after skipping, (WDF1) 0 Ceramic resonator selected RC oscillation selected (A) (MR) (MR) (A)
CMCK CRCK TAMR TMRA
1 1 1 1
0 0 0 0
1 1 0 0
0 0 1 0
0 0 0 0
1 1 1 1
1 1 0 0
0 0 0 1
1 1 1 1
0 1 0 0
29A 29B 252 216
1 1 1 1
1 1 1 1
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-98
HARDWARE 4506 Group INSTRUCTIONS
Skip condition
Carry flag CY
Datailed description
-
-
In the A/D conversion mode (Q13 = 0), transfers the high-order 4 bits (AD9-AD6) of register AD to register B, and the middle-order 4 bits (AD5-AD2) of register AD to register A. In the comparator mode (Q13 = 1), transfers the high-order 4 bits (AD7-AD4) of comparator register to register B, and the low-order 4 bits (AD3-AD0) of comparator register to register A. (Q13: bit 3 of A/D control register Q1) Transfers the low-order 2 bits (AD1, AD0) of register AD to the high-order 2 bits (AD3, AD2) of register A. In the A/D conversion mode (Q13 = 0), this instruction is equivalent to the NOP instruction. In the comparator mode (Q13 = 1), transfers the contents of register B to the high-order 4 bits (AD7-AD4) of comparator register, and the contents of register A to the low-order 4 bits (AD3-AD0) of comparator register. (Q13 = bit 3 of A/D control register Q1) Transfers the contents of A/D control register Q1 to register A. Transfers the contents of register A to A/D control register Q1. Clears (0) to A/D conversion completion flag ADF, and the A/D conversion at the A/D conversion mode (Q13 = 0) or the comparator operation at the comparator mode (Q13 = 1) is started. (Q13 = bit 3 of A/D control register Q1) When V22 = 0 : Skips the next instruction when A/D conversion completion flag ADF is "1." After skipping, clears (0) to the ADF flag. When the ADF flag is "0," executes the next instruction. When V22 = 1 : This instruction is equivalent to the NOP instruction. (V22: bit 2 of interrupt control register V2) No operation; Adds 1 to program counter value, and others remain unchanged. Puts the system in RAM back-up state by executing the POF2 instruction after executing the EPOF instruction. Operations of all functions are stopped. Makes the immediate after POF2 instruction valid by executing the EPOF instruction. Skips the next instruction when the P flag is "1". After skipping, the P flag remains unchanged. Executes the next instruction when the P flag is "0." Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction. Skips the next instruction when watchdog timer flag WDF1 is "1." After skipping, clears (0) to the WDF1 flag. When the WDF1 flag is "0," executes the next instruction. Also, stops the watchdog timer function when executing the WRST instruction immediately after the DWDT instruction. Selects the ceramic resonance circuit and stops the on-chip oscillator. Selects the RC oscillation circuit and stops the on-chip oscillator. Transfers the contents of clock control register MR to register A. Transfers the contents of register A to clock control register MR.
- -
- -
- - -
- - -
V22 = 0: (ADF) = 1
-
- - - (P) = 1
- - - -
- (WDF1) = 1
- -
- - - -
- - - -
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-99
HARDWARE 4506 Group INSTRUCTIONS
INSTRUCTION CODE TABLE
D9-D4 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 D3-D0 notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F
Hex.
010000 011000 010111 011111
00 NOP - -
01 BLA CLD -
02
03
04 - - - - RT
05 TASP TAD TAX TAZ TAV1
06 A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 9 A 10 A 11 A 12 A 13 A 14 A 15
07 LA 0 LA 1 LA 2 LA 3 LA 4 LA 5 LA 6 LA 7 LA 8 LA 9 LA 10 LA 11 LA 12 LA 13 LA 14 LA 15
08
09
0A - - - - - - - - - - - - - - - -
0B - - - - - - - - - - - - - - - -
0C
0D
0E BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL
0F BL* BL* BL* BL* BL* BL* BL* BL* BL* BL* BL* BL* BL* BL* BL* BL*
10-17 18-1F BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM B B B B B B B B B B B B B B B B
SZB BMLA 0 SZB 1 SZB 2 SZB 3 SZD SEAn SEAM - - TDA - - - - - - - SNZ0 -
TABP TABP 0 16* TABP TABP 1 17* TABP TABP 2 18* TABP TABP 3 19* TABP TABP 4 20* TABP TABP 5 21* TABP TABP 6 22* TABP TABP 7 23* TABP TABP 8 24* TABP TABP 9 25* TABP TABP 10 26* TABP TABP 11 27* TABP TABP 12 28* TABP TABP 13 29* TABP TABP 14 30* TABP TABP 15 31*
BML BML* BML BML* BML BML* BML BML* BML BML* BML BML* BML BML* BML BML* BML BML* BML BML* BML BML* BML BML* BML BML* BML BML* BML BML* BML BML*
SNZP INY DI EI RC SC RD SD - DEY
RTS TAV2 RTI - LZ 0 LZ 1 LZ 2 LZ 3 RB 0 RB 1 RB 2 RB 3 - - - - - EPOF SB 0 SB 1 SB 2 SB 3
POF2 AND - AM AMC TYA - TBA - OR
TEAB TABE SNZI0 - CMA RAR TAB TAY - - - - - - - TV2A
SZC TV1A
The above table shows the relationship between machine language codes and machine language instructions. D3-D0 show the low-order 4 bits of the machine language code, and D9-D4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked "-." The codes for the second word of a two-word instruction are described below. The second word 10 0aaa aaaa 10 0aaa aaaa 10 0p00 pppp 10 0p00 pppp 00 0111 nnnn 00 0010 1011 * * cannot be used in the M34506M2-XXXFP.
BL BML BLA BMLA SEA SZD
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-100
HARDWARE 4506 Group INSTRUCTIONS
INSTRUCTION CODE TABLE (continued)
D9-D4 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 D3-D0 notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F
Hex.
110000 111111
20 - - - -
21 - - - TW6A
22
23
24 - - - - TAQ1 - - - -
25
26
27
28
29 - - - - - - - - - - CMCK CRCK
2A WRST - - - - - - - - - - - - - - -
2B TMA 0 TMA 1 TMA 2 TMA 3 TMA 4 TMA 5 TMA 6 TMA 7 TMA 8 TMA 9 TMA 10 TMA 11 TMA 12 TMA 13 TMA 14 TMA 15
2C
2D
2E
2F
30-3F
OP0A T1AB OP1A T2AB OP2A - - - - - - - - - - TPU0A TPU1A - - - - - - -
TAW6 IAP0 TAB1 SNZT1 - IAP1 TAB2 SNZT2 - - - - - - - - - - - - SNZAD -
TAM XAM XAMI XAMD LXY 0 0 0 0 TAM XAM XAMI XAMD LXY 1 1 1 1 TAM XAM XAMI XAMD LXY 2 2 2 2 TAM XAM XAMI XAMD LXY 3 3 3 3 TAM XAM XAMI XAMD LXY 4 4 4 4 TAM XAM XAMI XAMD LXY 5 5 5 5 TAM XAM XAMI XAMD LXY 6 6 6 6 TAM XAM XAMI XAMD LXY 7 7 7 7 TAM XAM XAMI XAMD LXY 8 8 8 8 TAM XAM XAMI XAMD LXY 9 9 9 9 TAM XAM XAMI XAMD LXY 10 10 10 10 TAM XAM XAMI XAMD LXY 11 11 11 11 TAM XAM XAMI XAMD LXY 12 12 12 12 TAM XAM XAMI XAMD LXY 13 13 13 13 TAM XAM XAMI XAMD LXY 14 14 14 14 TAM XAM XAMI XAMD LXY 15 15 15 15
TAMR IAP2 TAI1 - - TAK0 - - - - - - - - - - - - - - IAK
TQ1A TK1A - - - - - - - - - TW1A TK2A TMRA TI1A - - - TK0A - - -
TADAB TALA TAK1 - - - - - - TAW1 TAW2 - - - TAK2 - - - - -
TABAD SNZCP - - - - - - - -
RCP DWDT SCP - - - - ADST
TW2A OKA TPU2ATR1AB
The above table shows the relationship between machine language codes and machine language instructions. D3-D0 show the loworder 4 bits of the machine language code, and D9-D4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked "-." The codes for the second word of a two-word instruction are described below. The second word 10 0aaa aaaa 10 0aaa aaaa 10 0p00 pppp 10 0p00 pppp 00 0111 nnnn 00 0010 1011
BL BML BLA BMLA SEA SZD
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-101
HARDWARE 4506 Group BUILT-IN PROM VERSION
BUILT-IN PROM VERSION
In addition to the mask ROM versions, the 4506 Group has the One Time PROM versions whose PROMs can only be written to and not be erased. The built-in PROM version has functions similar to those of the mask ROM versions, but it has PROM mode that enables writing to built-in PROM. Table 20 shows the product of built-in PROM version. Figure 54 shows the pin configurations of built-in PROM versions. The One Time PROM version has pin-compatibility with the mask ROM version. Table 20 Product of built-in PROM version PROM size Part number ( 10 bits) M34506E4FP 4096 words
RAM size ( 4 bits) 256 words
Package PRSP0020DA-A
ROM type One Time PROM [shipped in blank]
(1) PROM mode
The 4506 Group has a PROM mode in addition to a normal operation mode. It has a function to serially input/output the command codes, addresses, and data required for operation (e.g., read and program) on the built-in PROM using only a few pins. This mode can be selected by setting pins SDA (serial data input/output), SCLK (serial clock input), PGM to "H" after connecting wires as shown in Figure 54 and powering on the VDD pin, and then applying 12 V to the VPP pin. In the PROM mode, three types of software commands (read, program, and program verify) can be used. Clock-synchronous serial I/O is used, beginning from the LSB (LSB first). Use the special-perpose serial programmer when performing serial read/program. As for the serial programmer for the single-chip microcomputer (serial programmer and control software), refer to the "Renesas Microcomputer Development Support Tools" Hompage (http:// www.renesas.com/en/tools).
Writing with PROM programmer
Screening (Leave at 150 C for 40 hours) (Note)
Verify test with PROM programmer
Function test in target device Note: Since the screening temperature is higher than storage temperature, never expose the microcomputer to 150 C exceeding 100 hours.
(2) Notes on handling
A high-voltage is used for writing. Take care that overvoltage is not applied. Take care especially at turning on the power. For the One Time PROM version shipped in blank, Renesas corp. does not perform PROM writing test and screening in the assembly process and following processes. In order to improve reliability after writing, performing writing and test according to the flow shown in Figure 53 before using is recommended (Products shipped in blank: PROM contents is not written in factory when shipped).
Fig. 53 Flow of writing and test of the product shipped in blank
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-102
HARDWARE 4506 Group BUILT-IN PROM VERSION
PIN CONFIGURATION (TOP VIEW)
VDD VSS
VDD VSS XIN XOUT
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
P00 P01 P02 P03 P10 P11 P12/CNTR P13/INT D0 D1
M34506E4FP
VPP
CNVSS RESET
SCLK SDA
PGM
P21/AIN1
VDD
P20/AIN0 D3/K D2/C
Outline PRSP0020DA-A (20P2N-A)
Fig. 54 Pin configuration of built-in PROM version
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
1-103
CHAPTER 2 APPLICATION
2.1 2.2 2.3 2.4 2.5 2.6 2.7 I/O pins Interrupts Timers A/D converter Reset RAM back-up Oscillation circuit
APPLICATION 4506 Group 2.1 I/O pins
2.1 I/O pins
The 4506 Group has the fourteen I/O pins. (Port P12 is also used as CNTR I/O pin, Port P13 is also used as INT input pin, Port P2 is also used as analog input pins AIN0 and AIN1, Port D2 is also used as Port C, and Port D3 is also used as Port K, respectively). This section describes each port I/O function, related registers, application example using each port function and notes. 2.1.1 I/O ports (1) Port P0 Port P0 is a 4-bit I/O port. Port P0 has the key-on wakeup function which turns ON/OFF with register K0 and pull-up transistor which turns ON/OFF with register PU0. s Input/output of port P0 q Data input to port P0 Set the output latch of specified port P0i (i=0 to 3) to "1" with the OP0A instruction. If the output latch is set to "0," "L" level is input. The state of port P0 is transferred to register A when the IAP0 instruction is executed. q Data output from port P0 The contents of register A is output to port P0 with the OP0A instruction. The output structure is an N-channel open-drain. (2) Port P1 Port P1 is a 4-bit I/O port. Port P1 has the key-on wakeup function which turns ON/OFF with register K1 and pull-up transistor which turns ON/OFF with register PU1. s Input/output of port P1 q Data input to port P1 Set the output latch of specified port P1i (i=0 to 3) to "1" with the OP1A instruction. If the output latch is set to "0," "L" level is input. The state of port P1 is transferred to register A when the IAP1 instruction is executed. q Data output from port P1 The contents of register A is output to port P1 with the OP1A instruction. The output structure is an N-channel open-drain. Note: Port P12 is also used as CNTR. Accordingly, when it is used as port P12, set "0" to the timer control register W60.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-2
APPLICATION 4506 Group 2.1 I/O pins
(3) Port P2 Port P2 is a 2-bit I/O port. Also, its key-on wakeup function is switched to ON/OFF by the register K20 and K21, and its pullup transistor function is switched to ON/OFF by the register PU20 and PU21. s Input/output of port P2 q Data input to port P2 Set the output latch of specified port P2i (i=0, 1) to "1" with the OP2A instruction. If the output latch is set to "0," "L" level is input. The state of port P2 is transferred to register A when the IAP2 instruction is executed. However, port P2 is 2 bits and A2 and A3 are fixed to "0." q Data output from port P2 The contents of register A is output to port P2 with the OP2A instruction. The output structure is an N-channel open-drain. (4) Port D D0-D3 are four independent I/O ports. Also, as for ports D2 and D3, its key-on wakeup function is switched to ON/OFF by the register K22 and K23, and its pull-up transistor function is switched to ON/OFF by the register PU22 and PU23. s Input/output of port D Each pin of port D has an independent 1-bit wide I/O function. For I/O of ports D0-D3, select one of port D with the register Y of the data pointer first. q Data input to port D Set the output latch of specified port Di (i = 0 to 3) to "1" with the SD instruction. When the output latch is set to "0," "L" level is input. When the SZD instruction is executed, if the port specified by register Y is "0," the next instruction is skipped. If it is "1," the next instruction is executed. q Data output from port D Set the output level to the output latch with the SD and RD instructions. The state of pin enters the high-impedance state when the SD instruction is executed. The states of all port D enter the high-impedance state when the CLD instruction is executed. The state of pin becomes "L" level when the RD instruction is executed. The output structure is an N-channel open-drain. Notes 1: When the SD and RD instructions are used, do not set "01002" or more to register Y. 2: Port D2 is also used as Port C. Accordingly, when using port D2, set the output latch to "1" with the SCP instruction. 3: Port D3 is also used as Port K. Accordingly, when using port D3, set the output latch to "1" with the OKA instruction.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-3
APPLICATION 4506 Group 2.1 I/O pins
(5) Port C Port C is a 1-bit I/O port. s Input/output of port C q Data input to port C Set the output latch of specified port C to "1" with the SCP instruction. If the output latch is set to "0," "L" level is input. When the SNZCP instruction is executed, if the port C is "1," the next instruction is skipped. If it is "0," the next instruction is executed. q Data output from port C Set the output level to the output latch with the SCP and RCP instructions. The state of pin enters the high-impedance state when the SCP instruction is executed. The state of pin becomes "L" level when the RCP instruction is executed. The output structure is an N-channel open-drain. Note: Port C is also used as port D2. Accordingly, when using port C, set the output latch to "1" with the SD instruction. (6) Port K Port K is a 1-bit I/O port. s Input/output of port K q Data input to port K Set the output latch of specified port K to "1" with the OKA instruction. If the output latch is set to "0," "L" level is input. The state of port K is transferred to register A when the IAK instruction is executed. However, port K is 1 bit and A1, A2 and A3 are fixed to "0." q Data output from port K The contents of register A is output to port K with the OKA instruction. The output structure is an N-channel open-drain. Note: Port K is also used as port D3. Accordingly, when using port K, set the output latch to "1" with the SD instruction.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-4
APPLICATION 4506 Group 2.1 I/O pins
2.1.2 Related registers (1) Key-on wakeup control register K0 Register K0 controls the ON/OFF of the key-on wakeup function of ports P00-P03. Set the contents of this register through register A with the TK0A instruction. The contents of register K0 is transferred to register A with the TAK0 instruction. Table 2.1.1 shows the key-on wakeup control register K0. Table 2.1.1 Key-on wakeup control register K0 Key-on wakeup control register K0 K03 K02 K01 K00 Port P03 key-on wakeup control bit Port P02 key-on wakeup control bit Port P01 key-on wakeup control bit Port P00 at reset : 00002 0 1 0 1 0 1 0 at RAM back-up : state retained R/W
Key-on wakeup invalid Key-on wakeup valid Key-on wakeup invalid Key-on wakeup valid Key-on wakeup invalid Key-on wakeup valid Key-on wakeup invalid
key-on wakeup control bit Key-on wakeup valid 1 Note: "R" represents read enabled, and "W" represents write enabled. (2) Pull-up control register PU0 Register PU0 controls the ON/OFF of the ports P00-P03 pull-up transistor. Set the contents of this register through register A with the TPU0A instruction. Table 2.1.2 shows the pull-up control register PU0. Table 2.1.2 Pull-up control register PU0 Pull-up control register PU0 PU03 PU02 PU01 PU00 Port P03 pull-up transistor control bit Port P02 pull-up transistor control bit Port P01 pull-up transistor control bit Port P00 at reset : 00002 0 1 0 1 0 1 0 1 at RAM back-up : state retained W
Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON
pull-up transistor control bit Note: "W" represents write enabled.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-5
APPLICATION 4506 Group 2.1 I/O pins
(3) Key-on wakeup control register K1 Register K1 controls the ON/OFF of the key-on wakeup function of ports P10-P13. Set the contents of this register through register A with the TK1A instruction. The contents of register K1 is transferred to register A with the TAK1 instruction. Table 2.1.3 shows the key-on wakeup control register K1. Table 2.1.3 Key-on wakeup control register K1 Key-on wakeup control register K1 K13 K12 K11 Port P13/INT key-on wakeup control bit Port P12/CNTR key-on wakeup control bit Port P11 key-on wakeup control bit Port P10 at reset : 00002 0 1 0 1 0 1 at RAM back-up : state retained R/W
P13 key-on wakeup invalid/INT pin key-on wakeup valid P13 key-on wakeup valid/INT pin key-on wakeup invalid Key-on wakeup invalid Key-on wakeup valid Key-on wakeup invalid
Key-on wakeup valid Key-on wakeup invalid 0 K10 Key-on wakeup valid key-on wakeup control bit 1 Note: "R" represents read enabled, and "W" represents write enabled. (4) Pull-up control register PU1 Register PU1 controls the ON/OFF of the ports P10-P13 pull-up transistor. Set the contents of this register through register A with the TPU1A instruction. Table 2.1.4 shows the pull-up control register PU1. Table 2.1.4 Pull-up control register PU1 Pull-up control register PU1 PU13 PU12 PU11 PU10 Port P13/INT pull-up transistor control bit Port P12/CNTR pull-up transistor control bit Port P11 pull-up transistor control bit Port P10 at reset : 00002 0 1 0 1 0 1 0 1 at RAM back-up : state retained W
Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON
pull-up transistor control bit Note: "W" represents write enabled.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-6
APPLICATION 4506 Group 2.1 I/O pins
(5) Key-on wakeup control register K2 Register K2 controls the ON/OFF of the key-on wakeup function of ports P20, P21, D2/C and D3/K. Set the contents of this register through register A with the TK2A instruction. The contents of register K2 is transferred to register A with the TAK2 instruction. Table 2.1.5 shows the key-on wakeup control register K2. Table 2.1.5 Key-on wakeup control register K2 Key-on wakeup control register K2 K23 K22 K21 Port D3/K key-on wakeup control bit Port D2/C key-on wakeup control bit Port P21/AIN1 key-on wakeup control bit Port P20/AIN0 at reset : 00002 0 1 0 1 0 1 at RAM back-up : state retained R/W
Key-on wakeup invalid Key-on wakeup valid Key-on wakeup invalid Key-on wakeup valid Key-on wakeup invalid
Key-on wakeup valid Key-on wakeup invalid 0 K20 Key-on wakeup valid key-on wakeup control bit 1 Note: "R" represents read enabled, and "W" represents write enabled. (6) Pull-up control register PU2 Register PU2 controls the ON/OFF of the ports P20, P21, D2/C and D3/K pull-up transistor. Set the contents of this register through register A with the TPU2A instruction. Table 2.1.6 shows the pull-up control register PU2. Table 2.1.6 Pull-up control register PU2 Pull-up control register PU2 PU23 PU22 PU21 PU20 Port D3/K pull-up transistor control bit Port D2/C pull-up transistor control bit Port P21/AIN1 pull-up transistor control bit Port P20/AIN0 at reset : 00002 0 1 0 1 0 1 0 1 at RAM back-up : state retained W
Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON
pull-up transistor control bit Note: "W" represents write enabled.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-7
APPLICATION 4506 Group 2.1 I/O pins
(7) Timer control register W6 Bit 0 of register W6 selects the P12/CNTR function, and bit 1 controls the CNTR output. Set the contents of this register through register A with the TW6A instruction. The contents of register W6 is transferred to register A with the TAW6 instruction. Table 2.1.7 shows the timer control register W6. Table 2.1.7 Timer control register W6 Timer control register W6 W63 W62 W61 W60 Not used Not used CNTR output control bit P12/CNTR function selection bit at reset : 00002 0 1 0 1 0 1 0 at RAM back-up : state retained R/W
This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. Timer 1 underflow signal divided by 2 output Timer 2 underflow signal divided by 2 output
P12 (I/O) / CNTR input 1 P12 (input) / CNTR input/output Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: When setting the port, W63-W61 are not used.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-8
APPLICATION 4506 Group 2.1 I/O pins
2.1.3 Port application examples (1) Key input by key scan Key matrix can be set up by connecting keys externally because port D output structure is an Nchannel open-drain and port P0 has the pull-up resistor. Outline: The connecting required external part is just keys. Specifications: Port D is used to output "L" level and port P0 is used to input 16 keys. Figure 2.1.1 shows the key input and Figure 2.1.2 shows the key input timing.
M34506
D0
SW4
SW3
SW2
SW1
SW8
SW7
SW6
SW5
D1
SW12 SW11 SW10 SW9
D2
SW16 SW15 SW14 SW13
D3
P00 P01 P02 P03
Fig. 2.1.1 Key input by key scan
Switching key input selection port (D 0 D 1) Stabilizing wait time for input Reading port (key input)
Key input period D0 D1 D2 D3 "H" "L " "H " "L" "H " "L " "H " "L" IAP0 Input to SW1-SW4 IAP0 Input to SW5-SW8 IAP0 Input to SW9-SW12 IAP0 Input to SW13-SW16 IAP0
Input to SW1-SW4
Note: "H" output of port D becomes high-impedance state.
Fig. 2.1.2 Key scan input timing
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-9
APPLICATION 4506 Group 2.1 I/O pins
2.1.4 Notes on use (1) Note when an I/O port is used as an input port Set the output latch to "1" and input the port value before input. If the output latch is set to "0," "L" level can be input. (2) Noise and latch-up prevention Connect an approximate 0.1 F bypass capacitor directly to the VSS line and the VDD line with the thickest possible wire at the shortest distance, and equalize its wiring in width and length. The CNVSS pin is also used as the VPP pin (programming voltage = 12.5 V) at the One Time PROM version. Connect the CNVSS/VPP pin to VSS through an approximate 5 k resistor which is connected to the CNVSS/VPP pin at the shortest distance. (3) Note on multifunction * The input/output of D2, D3, P12 and P13 can be used even when C, K, CNTR (input) and INT are selected. * The input of P12 can be used even when CNTR (output) is selected. * The input/output of P20 and P21 can be used even when AIN0 and AIN1 are selected. (4) Connection of unused pins Table 2.1.8 shows the connections of unused pins. (5) SD, RD instructions When the SD and RD instructions are used, do not set "01002" or more to register Y. (6) Analog input pins When both analog input AIN0 and AIN1 and I/O port P2 function are used, note the following; * Selection of analog input pins Even when P20/AIN0 and P21/AIN1 are set to pins for analog input, they continue to function as port P2 input/output. Accordingly, when any of them are used as I/O port and others are used as analog input pins, make sure to set the outputs of pins that are set for analog input to "1." Also, the port input function of the pin functions as an analog input is undefined. (7) Notes on port P13/INT pin When the bit 3 of register I1 is cleared, the RAM back-up mode is selected and the input of INT pin is disabled, be careful about the following notes. * When the key-on wakeup function of port P13 is not used (register K13 = "0"), clear bits 2 and 3 of register I1 before system enters to the RAM back-up mode.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-10
APPLICATION 4506 Group 2.1 I/O pins
Table 2.1.8 Connections of unused pins Connection Pin Connect to VSS. XIN Open. XOUT
Usage condition System operates by the on-chip oscillator. (Note 1) System operates by the external clock. (The ceramic resonator is selected with the CMCK instruction.) System operates by the RC oscillator. (The RC oscillation is selected with the CRCK instruction.) System operates by the on-chip oscillator. (Note 1)
D0, D1
D2/C D3/K
Open. (Output latch Open. (Output latch Connect to VSS. Open. (Output latch Open. (Output latch Connect to VSS.
is set to "1.") is set to "0.") is set to "1.") The key-on wakeup function is not selected. (Note 4) is set to "0.") The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3) The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3) is set to "1.") The key-on wakeup function is not selected. (Note 4) is set to "0.") The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3) The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3) is set to "1.") The key-on wakeup function is not selected. (Note 4) is set to "0.") The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3) The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3) is set to "1.") The key-on wakeup function is not selected. The input to INT pin is disabled. (Notes 4, 5) is set to "0.") The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3) The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3) is set to "1.") The key-on wakeup function is not selected. (Note 4) is set to "0.") The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3) The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3)
P00-P03
Open. (Output latch Open. (Output latch Connect to VSS.
P10, P11 Open. (Output latch P12/CNTR Open. (Output latch Connect to VSS. P13/INT Open. (Output latch Open. (Output latch Connect to VSS. P20/AIN0 P21/AIN1 Open. (Output latch Open. (Output latch Connect to VSS.
Notes 1: When the ceramic resonator or the RC oscillation is not selected by program, system operates by the on-chip oscillator (internal oscillator). 2: When the pull-up function is left valid, the supply current is increased. Do not select the pull-up function. 3: When the key-on wakeup function is left valid, the system returns from the RAM back-up state immediately after going into the RAM back-up state. Do not select the key-on wakeup function. 4: When selecting the key-on wakeup function, select also the pull-up function. 5: Clear the bit 3 (I13) of register I1 to "0" to disable to input to INT pin (after reset: I13 = "0") (Note when connecting to VSS) q Connect the unused pins to VSS using the thickest wire at the shortest distance against noise.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-11
APPLICATION 4506 Group 2.2 Interrupts
2.2 Interrupts
The 4506 Group has four interrupt sources : external (INT), timer 1, timer 2, and A/D. This section describes individual types of interrupts, related registers, application examples using interrupts and notes. 2.2.1 Interrupt functions (1) External 0 interrupt (INT) The interrupt request occurs by the change of input level of INT pin. The interrupt valid waveform can be selected by the bits 1 and 2, and the INT pin input is controlled by the bit 3 of the interrupt control register I1. s External 0 interrupt INT processing q When the interrupt is used The interrupt occurrence is enabled when the bit 0 of the interrupt control register V1 and the interrupt enable flag INTE are set to "1." When the external 0 interrupt occurs, the interrupt processing is executed from address 0 in page 1. q When the interrupt is not used The interrupt is disabled and the SNZ0 instruction is valid when the bit 0 of register V1 is set to "0." (2) Timer 1 interrupt The interrupt request occurs by the timer 1 underflow. s Timer 1 interrupt processing q When the interrupt is used The interrupt occurrence is enabled when the bit 2 of the interrupt control register V1 and the interrupt enable flag INTE are set to "1." When the timer 1 interrupt occurs, the interrupt processing is executed from address 4 in page 1. q When the interrupt is not used The interrupt is disabled and the SNZT1 instruction is valid when the bit 2 of register V1 is set to "0." (3) Timer 2 interrupt The interrupt request occurs by the timer 2 underflow. s Timer 2 interrupt processing q When the interrupt is used The interrupt occurrence is enabled when the bit 3 of the interrupt control register V1 and the interrupt enable flag INTE are set to "1." When the timer 2 interrupt occurs, the interrupt processing is executed from address 6 in page 1. q When the interrupt is not used The interrupt is disabled and the SNZT2 instruction is valid when the bit 3 of register V1 is set to "0."
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-12
APPLICATION 4506 Group 2.2 Interrupts
(4) A/D interrupt The interrupt request occurs by the end of the A/D conversion. s A/D interrupt processing q When the interrupt is used The interrupt occurrence is enabled when the bit 2 of the interrupt control register V2 and the interrupt enable flag INTE are set to "1." When the A/D interrupt occurs, the interrupt processing is executed from address C in page 1. q When the interrupt is not used The interrupt is disabled and the SNZAD instruction is valid when the bit 2 of register V2 is set to "0." 2.2.2 Related registers (1) Interrupt enable flag (INTE) The interrupt enable flag (INTE) controls whether the every interrupt enable/disable. Interrupts are enabled when INTE flag is set to "1" with the EI instruction and disabled when INTE flag is cleared to "0" with the DI instruction. When any interrupt occurs, the INTE flag is automatically cleared to "0," so that other interrupts are disabled until the EI instruction is executed. Note: The interrupt enabled with the EI instruction is performed after the EI instruction and one more instruction. (2) Interrupt control register V1 Interrupt enable bit of external 0, timer 1 and timer 2 are assigned to register V1. Set the contents of this register through register A with the TV1A instruction. In addition, the TAV1 instruction can be used to transfer the contents of register V1 to register A. Table 2.2.1 shows the interrupt control register V1. Table 2.2.1 Interrupt control register V1 Interrupt control register V1 V13 V12 V11 V10 Timer 2 interrupt enable bit Timer 1 interrupt enable bit Not used External 0 interrupt enable bit at reset : 00002 0 1 0 1 0 1 0 1 at RAM back-up : 00002 R/W
Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) (Note 2) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) (Note 2) This bit has no function, but read/write is enabled. Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) (Note 2)
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: These instructions are equivalent to the NOP instruction. 3: When the interrupt is set, V11 is not used.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-13
APPLICATION 4506 Group 2.2 Interrupts
(3) Interrupt control register V2 Interrupt enable bit of A/D is assigned to register V2. Set the contents of this register through register A with the TV2A instruction. In addition, the TAV2 instruction can be used to transfer the contents of register V2 to register A. Table 2.2.2 shows the interrupt control register V2. Table 2.2.2 Interrupt control register V2 Interrupt control register V2 V23 V22 V21 V20 Not used A/D interrupt enable bit Not used Not used at reset : 00002 0 1 0 1 0 1 0 1 at RAM back-up : 00002 R/W
This bit has no function, but read/write is enabled. Interrupt disabled (SNZAD instruction is valid) Interrupt enabled (SNZAD instruction is invalid) (Note 2) This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled.
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: This instruction is equivalent to the NOP instruction. 3: When the interrupt is set, V23, V21 and V20 are not used. (4) Interrupt request flag The activated condition for each interrupt is examined. Each interrupt request flag is set to "1" when the activated condition is satisfied, even if the interrupt is disabled by the INTE flag or its interrupt enable bit. Each interrupt request flag is cleared to "0" when either; *an interrupt occurs, or *the next instruction is skipped with a skip instruction.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-14
APPLICATION 4506 Group 2.2 Interrupts
(5) Interrupt control register I1 The INT pin timer 1 control enable bit is assigned to bit 0, INT pin edge detection circuit control bit is assigned to bit 1, interrupt valid waveform for INT pin/return level selection bit is assigned to bit 2 and INT pin input control bit is assigned to bit 3. Set the contents of this register through register A with the TI1A instruction. In addition, the TAI1 instruction can be used to transfer the contents of register I1 to register A. Table 2.2.3 shows the interrupt control register I1. Table 2.2.3 Interrupt control register I1 Interrupt control register I1 I13 INT pin input control bit (Note 2) Interrupt valid waveform for INT pin/return level selection bit (Note 2) INT pin edge detection circuit control bit INT pin at reset : 00002 0 1 0 1 0 1 0 at RAM back-up : state retained R/W
INT pin input disabled INT pin input enabled Falling waveform ("L" level of INT pin is recognized with the SNZI0 instruction)/"L" level Rising waveform ("H" level of INT pin is recognized with the SNZI0 instruction)/"H" level One-sided edge detected Both edges detected Disabled
I12
I11 I10
Enabled timer 1 control enable bit 1 Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction when the bit 0 (V10) of register V1 to "0". In this time, set the NOP instruction after the SNZ0 instruction, for the case when a skip is performed with the SNZ0 instruction.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-15
APPLICATION 4506 Group 2.2 Interrupts
2.2.3 Interrupt application examples (1) INT interrupt The INT pin is used for external 0 interrupt, of which valid waveforms can be chosen, which can recognize the change of both edges ("H""L" or "L""H"). Outline: An external 0 interrupt can be used by dealing with the change of edge ("H""L" or "L""H") in both directions as a trigger. Specifications: An interrupt occurs by the change of an external signals edge ("H""L" or "L""H"). Figure 2.2.1 shows an operation example of an external 0 interrupt, and Figure 2.2.2 shows a setting example of an external 0 interrupt. (2) Timer 1 interrupt Constant period interrupts by a setting value to timer 1 can be used. Outline: The constant period interrupts by the timer 1 underflow signal can be used. Specifications: Prescaler and timer 1 divide the system clock frequency f(XIN) = 4.0 MHz, and the timer 1 interrupt occurs every 1 ms. Figure 2.2.3 shows a setting example of the timer 1 constant period interrupt. (3) Timer 2 interrupt Constant period interrupts by a setting value to timer 2 can be used. Outline: The constant period interrupts by the timer 2 underflow signal can be used. Specifications: Timer 2 and prescaler divide the system clock frequency (= 4.0 MHz), and the timer 2 interrupt occurs every about 1 ms. Figure 2.2.4 shows a setting example of the timer 2 constant period interrupt.
P13/INT
"H" "L"
P13/INT
"H" "L"
An interrupt occurs after the valid waveform "falling" is detected. An interrupt occurs after the valid waveform "rising" is detected.
Fig. 2.2.1 INT interrupt operation example
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-16
APPLICATION 4506 Group 2.2 Interrupts
Disable Interrupts
INT interrupt is temporarily disabled. Interrupt enable flag INTE "0"
b3
Interrupt control register V1
All interrupts disabled (DI instruction) INT interrupt occurrence disabled 0 (TV1A instruction)
b0
Set Port
Port used for INT interrupt is set to input port.
b3 b0
Port P13 output latch
1 Set to input (OP1A instruction)
Set Valid Waveform
Valid waveform of INT pin is selected. Both edges detection selected b3 b0 Interrupt control register I1 1 1 Both edges detection selected (TI1A instruction)
Execute NOP Instruction
NOP instruction
Clear Interrupt Request
INT interrupt activated condition is cleared. INT interrupt request flag EXF0 "0" INT interrupt activated condition cleared (SNZ0 instruction)
Note when the interrupt request is cleared
When is executed, considering the skip of the next instruction according to the interrupt request flag EXF0, insert the NOP instruction after the SNZ0 instruction.
Enable Interrupts
The INT interrupt which is temporarily disabled is enabled. b3 b0 Interrupt control register V1 1 INT interrupt occurrence enabled (TV1A instruction) Interrupt enable flag INTE "1" All interrupts enabled (EI instruction)
INT interrupt execution started
"": it can be "0" or "1."
Fig. 2.2.2 INT interrupt setting example Note: The valid waveforms causing the interrupt must be retained at their level for 4 cycles or more of system clock.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-17
APPLICATION 4506 Group 2.2 Interrupts
Disable Interrupts
Timer 1 interrupt is temporarily disabled. Interrupt enable flag INTE "0"
b3
Interrupt control register V1
All interrupts disabled (DI instruction) Timer 1 interrupt occurrence disabled 0 (TV1A instruction)
b0
Stop Timer Operation
Timer 1 and prescaler are temporarily stopped. Dividing ratio of prescaler is selected.
b3 b0
Timer 1 stop (TW1A instruction) Prescaler divided by 16 selected
Timer control register W1
0 1 0 0 Prescaler stop
Set Timer Value
Timer 1 count time is set. (The formula is shown A below.) Timer 1 reload register R1 "5216" Timer count value 82 set (T1AB instruction)
Clear Interrupt Request
Timer 1 interrupt activated condition is cleared. Timer 1 interrupt request flag T1F "0" Timer 1 interrupt activated condition cleared (SNZT1 instruction)
Note when the interrupt request is cleared
When is executed, considering the skip of the next instruction according to the interrupt request flag T1F, insert the NOP instruction after the SNZT1 instruction.
Start Timer Operation
Timer 1 and prescaler temporarily stopped are restarted.
b3 b0
Timer control register W1 1 1 1 0
Timer 1 operation start (TW1A instruction) Prescaler operation start
Enable Interrupts
The Timer 1 interrupt which is temporarily disabled is enabled. b3 b0 Timer 1 interrupt occurrence enabled Interrupt control register V1 1 (TV1A instruction) Interrupt enable flag INTE "1" All interrupts enabled (EI instruction)
Constant period interrupt execution start
A The prescaler dividing ratio and timer 1 count value to make the interrupt occur every 1 ms are set as follows.
1 ms (4.0 MHz) 3 16 System clock Instruction Prescaler clock dividing ratio
-1
(82+1) Timer 1 count value
"": it can be "0" or "1."
Fig. 2.2.3 Timer 1 constant period interrupt setting example
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-18
APPLICATION 4506 Group 2.2 Interrupts
Disable Interrupts
Timer 2 interrupt is temporarily disabled. Interrupt enable flag INTE "0"
b3
All interrupts disabled (DI instruction) Timer 2 interrupt occurrence disabled Interrupt control register V1 0 (TV1A instruction)
b0
Stop Timer 2 Operation
Timer 2 and prescaler are temporarily stopped. Dividing ratio of prescaler is selected. b3 b0 Prescaler stop (TW1A instruction) Timer control register W1 0 1 Prescaler divided by 16 selected for count source
b3 b0
Timer control register W2 0 0 1
Timer 2 stop (TW2A instruction) Prescaler output selected for count source
Set Timer Value
Timer 2 count time is set. (The formula is shown A below.) Timer 2 reload register R2 "5216" Timer count value 82 set (T2AB instruction)
Clear Interrupt Request
Timer 2 interrupt activated condition is cleared. Timer 2 interrupt request flag T2F "0" Timer 2 interrupt activated condition cleared (SNZT2 instruction)
Note when the interrupt request is cleared
When is executed, considering the skip of the next instruction according to the interrupt request flag T2F, insert the NOP instruction after the SNZT2 instruction.
Start Timer 2 Operation
Timer 2 and prescaler temporarily stopped are restarted.
b3 b0
Timer control register W2 1 0 1 Timer 2 operation start (TW2A instruction)
b3 b0
Timer control register W1 1 1 Prescaler operation start (TW1A instruction)
Enable Interrupts
The timer 2 interrupt which is temporarily disabled is enabled. b3 b0 Timer 2 interrupt occurrence enabled Interrupt control register V1 1 (TV1A instruction) Interrupt enable flag INTE "1" All interrupts enabled (EI instruction)
Constant period interrupt execution start
A The prescaler dividing ratio and timer 2 count value to make the interrupt occur every about 1 ms is set as follows.
1 ms (4.0 MHz) 3 16 System clock Instruction Prescaler dividing clock ratio
-1
(82+1) Timer 2 count value
"": it can be "0" or "1."
Fig. 2.2.4 Timer 2 constant period interrupt setting example
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-19
APPLICATION 4506 Group 2.2 Interrupts
2.2.4 Notes on use (1) Setting of INT interrupt valid waveform Set a value to the bit 2 of register I1, and execute the SNZ0 instruction to clear the EXF0 flag to "0" after executing at least one instruction. Depending on the input state of P13/INT pin, the external interrupt request flag (EXF0) may be set to "1" when the interrupt valid waveform is changed. (2) Setting of INT pin input control Set a value to the bit 3 of register I1, and execute the SNZ0 instruction to clear the EXF0 flag to "0" after executing at least one instruction. Depending on the input state of P13/INT pin, the external interrupt request flag (EXF0) may be set to "1" when the interrupt valid waveform is changed. (3) Multiple interrupts Multiple interrupts cannot be used in the 4506 Group. (4) Notes on interrupt processing When the interrupt occurs, at the same time, the interrupt enable flag INTE is cleared to "0" (interrupt disable state). In order to enable the interrupt at the same time when system returns from the interrupt, write EI and RTI instructions continuously. (5) P13/INT pin The P13/INT pin need not be selected the external interrupt input INT function or the normal output port P13 function. However, the EXF0 flag is set to "1" when a valid waveform is input to INT pin even if it is used as an I/O port P13. (6) Power down instruction Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-20
APPLICATION 4506 Group 2.3 Timers
2.3 Timers
The 4506 Group has two 8-bit timers (each has a reload register) and a 16-bit fixed dividing frequency timer which has the watchdog timer function. This section describes individual types of timers, related registers, application examples using timers and notes. 2.3.1 Timer functions (1) Timer 1 s Timer operation (Timer 1 has the timer 1 count start trigger function from P13/INT pin input) (2) Timer 2 s Timer operation (3) 16-bit timer s Watchdog function Watchdog timer provides a method to reset the system when a program run-away occurs. System operates after it is released from reset. When the timer count value underflows, the WDF1 flag is set to "1." Then, if the WRST instruction is never executed until timer WDT counts 65534, WDF2 flag is set to "1," and system reset occurs. When the DWDT instruction and the WRST instruction are executed continuously, the watchdog timer function is invalid. The WRST instruction has the skip function. When the WRST instruction is executed while the WDF1 flag is "1", the WDF1 flag is cleared to "0" and the next instruction is skipped.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-21
APPLICATION 4506 Group 2.3 Timers
2.3.2 Related registers (1) Interrupt control register V1 The external 0 interrupt enable bit is assigned to bit 0, timer 1 interrupt enable bit is assigned to bit 2, and the timer 2 interrupt enable bit is assigned to bit 3. Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction can be used to transfer the contents of register V1 to register A. Table 2.3.1 shows the interrupt control register V1. Table 2.3.1 Interrupt control register V1 Interrupt control register V1 V13 V12 V11 V10 Timer 2 interrupt enable bit Timer 1 interrupt enable bit Not used External 0 interrupt enable bit at reset : 00002 0 1 0 1 0 1 0 at RAM back-up : 00002 R/W
Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) (Note 2) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) (Note 2) This bit has no function, but read/write is enabled. Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid) (Note 2) 1 Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: These instructions are equivalent to the NOP instruction. 3: When timer is used, V11 and V10 are not used. (2) Timer control register W1 The timer 1 count start synchronous circuit control bit is assigned to bit 0, the timer 1 control bit is assigned to bit 1, the prescaler dividing ratio selection bit is assigned to bit 2, and the prescaler control bit is assigned to bit 3. Set the contents of this register through register A with the TW1A instruction. The TAW1 instruction can be used to transfer the contents of register W1 to register A. Table 2.3.2 shows the timer control register W1. Table 2.3.2 Timer control register W1 Timer control register W1 W13 W12 W11 W10 Prescaler control bit Prescaler dividing ratio selection bit Timer 1 control bit Timer 1 count start synchronous circuit control bit at reset : 00002 0 1 0 1 0 1 0 1 at RAM back-up : 00002 R/W
Stop (state initialized) Operating Instruction clock divided by 4 Instruction clock divided by 16 Stop (state retained) Operating Count start synchronous circuit not selected Count start synchronous circuit selected
Note: "R" represents read enabled, and "W" represents write enabled.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-22
APPLICATION 4506 Group 2.3 Timers
(3) Timer control register W2 The timer 2 count source selection bits are assigned to bits 0 and 1, the timer 1 count auto-stop circuit control bit is assigned to bit 2 and the timer 2 control bit is assigned to bit 3. Set the contents of this register through register A with the TW2A instruction. The TAW2 instruction can be used to transfer the contents of register W2 to register A. Table 2.3.3 shows the timer control register W2. Table 2.3.3 Timer control register W2 Timer control register W2 W23 W22 Timer 2 control bit Timer 1 count auto-stop circuit control bit (Note 2) at reset : 00002 0 1 0 at RAM back-up : state retained R/W
Stop (state retained) Operating Count auto-stop circuit not selected Count auto-stop circuit selected Count source Timer 1 underflow signal Prescaler output (ORCLK) CNTR input
W21
W20
System clock Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: This function is valid only when the timer 1 count start synchronous circuit is selected. (4) Timer control register W6 The P12/CNTR function selection bit is assigned to bit 0 and the CNTR output control bit is assigned to bit 1. Set the contents of this register through register A with the TW6A instruction. The TAW6 instruction can be used to transfer the contents of register W6 to register A. Table 2.3.4 shows the timer control register W6. Table 2.3.4 Timer control register W6 Timer control register W6 W63 W62 W61 W60 Not used Not used CNTR output control bit P12/CNTR function selection bit at reset : 00002 0 1 0 1 0 1 0 1 at RAM back-up : state retained R/W
1 W21 W20 0 0 Timer 2 count source selection 0 1 bits 1 0 1 1
This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. Timer 1 underflow signal divided by 2 output Timer 2 underflow signal divided by 2 output P12 (I/O) / CNTR input (Note 2) P12 (input) / CNTR I/O (Note 2)
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: The CNTR input is valid only when the CNTR input is selected for the timer 2 count source. 3: When timer is used, W63 and W62 are not used.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-23
APPLICATION 4506 Group 2.3 Timers
2.3.3 Timer application examples (1) Timer operation: measurement of constant period The constant period by the setting timer count value can be measured. Outline: The constant period by the timer 1 underflow signal can be measured. Specifications: Timer 1 and prescaler divides the system clock frequency f(XIN) = 4.0 MHz, and the timer 1 interrupt request occurs every 3 ms. Figure 2.3.3 shows the setting example of the constant period measurement. (2) CNTR output operation: piezoelectric buzzer output Outline: Square wave output from timer 1 can be used for piezoelectric buzzer output. Specifications: 4 kHz square wave is output from the CNTR pin at system clock frequency f(XIN) = 4.0 MHz. Also, timer 1 interrupt occurs simultaneously. Figure 2.3.1 shows the peripheral circuit example, and Figure 2.3.4 shows the setting example of CNTR output.
In order to reduce the current dissipation, output is high-impedance state during buzzer output stop.
4506
125 s 125 s Set dividing ratio for timer 1 underflow cycle to 125 s.
CNTR
Fig. 2.3.1 Peripheral circuit example (3) CNTR input operation: event count Outline: Count operation can be performed by using the signal (falling waveform) input from CNTR pin as the event. Specifications: The low-frequency pulse from external as the timer 2 count source is input to CNTR pin, and the timer 2 interrupt request occurs every 100 counts. Figure 2.3.5 shows the setting example of CNTR input.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-24
APPLICATION 4506 Group 2.3 Timers
(4) Timer operation: timer start by external input Outline: The constant period can be measured by external input. Specifications: System clock frequency f(XIN) = 4 MHz and timer 1 operates by INT input as a trigger and an interrupt occurs after 1 ms. Figure 2.3.6 shows the setting example of timer start. (5) Watchdog timer Watchdog timer provides a method to reset the system when a program run-away occurs. Accordingly, when the watchdog timer function is set to be valid, execute the WRST instruction at a certain period which consists of timer 16-bit timers' 65534 counts or less (execute WRST instruction at a cycle of 65534 machine cycles or less). Outline: Execute the WRST instruction in 16-bit timer's 65534 counts at the normal operation. If a program runs incorrectly, the WRST instruction is not executed and system reset occurs. Specifications: System clock frequency f(XIN) = 4.0 MHz is used, and program run-away is detected by executing the WRST instruction in 49 ms. Figure 2.3.2 shows the watchdog timer function, and Figure 2.3.7 shows the example of watchdog timer.
FFFF16 Value of 16-bit timer (WDT) 000016 WDF1 flag
65534 count (Note) WDF2 flag
RESET pin output Reset released WRST instruction executed (skip executed) System reset
After system is released from reset (= after program is started), timer WDT starts count down. When timer WDT underflow occurs, WDF1 flag is set to "1." When the WRST instruction is executed, WDF1 flag is cleared to "0," the next instruction is skipped. When timer WDT underflow occurs while WDF1 flag is "1," WDF2 flag is set to "1" and the watchdog reset signal is output. The output transistor of RESET pin is turned "ON" by the watchdog reset signal and system reset is executed. Note: The number of count is equal to the number of machine cycle because the count source of watchdog timer is the instruction clock.
Fig. 2.3.2 Watchdog timer function
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-25
APPLICATION 4506 Group 2.3 Timers
Disable Interrupts
Timer 1 interrupt is temporarily disabled. Interrupt enable flag INTE "0"
b3
Interrupt control register V1
All interrupts disabled (DI instruction) Timer 1 interrupt occurrence disabled 0 (TV1A instruction)
b0
Stop Timer Operation
Timer 1 and prescaler are temporarily stopped. Dividing ratio of prescaler is selected.
b3 b0
Timer control register W1
0 1 00
Timer 1 stop (TW1A instruction) Prescaler stop Prescaler divided by 16 selected
Set Timer Value
Timer 1 count time is set. (The formula is shown A below.) Timer 1 reload register R1 "F916" Timer count value 249 set (T1AB instruction)
Clear Interrupt Request
Timer 1 interrupt activated condition is cleared. Timer 1 interrupt request flag T1F "0" Timer 1 interrupt activated condition cleared (SNZT1 instruction)
Note when the interrupt request is cleared
When is executed, considering the skip of the next instruction according to the interrupt request flag T1F, insert the NOP instruction after the SNZT1 instruction.
Start Timer 1 Operation
Timer 1 and prescaler temporarily stopped are restarted.
b3 b0
Timer control register W1 1 1 1 0 Timer 1 operation start (TW1A instruction) Prescaler operation start
Enable Interrupts
The timer 1 interrupt which is temporarily disabled is enabled. b3 b0 Timer 1 interrupt occurrence enabled Interrupt control register V1 1 (TV1A instruction) "1" All interrupts enabled (EI instruction) Interrupt enable flag INTE
Constant period interrupt execution start
A The prescaler dividing ratio and timer 1 count value to make the interrupt occur every 3 ms are set as follows.
3 ms = (4.0 MHz) System clock
-1
3 16 Instruction Prescaler clock dividing ratio
(249+1) Timer 1 count value
"": it can be "0" or "1."
Fig. 2.3.3 Constant period measurement setting example
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-26
APPLICATION 4506 Group 2.3 Timers
Disable Interrupts
Timer 1 interrupt is temporarily disabled. Interrupt enable flag INTE "0"
b3 b0
All interrupts disabled (DI instruction) Timer 1 interrupt occurrence disabled (TV1A instruction)
Interrupt control register V1
0
Stop Timer Operation
Timer 1 and prescaler are temporarily stopped. Dividing ratio of prescaler is selected.
b3 b0
Timer control register W1
0000
Timer 1 stop (TW1A instruction) Prescaler stop Prescaler divided by 4 selected
Set Timer Value, Select CNTR Output
CNTR output is selected. Timer 1 count time is set.
b3 b0
Timer control register W6 0 1 CNTR output selected (TW6A instruction) Timer 1 reload register R1 "2916" Timer count value 41 set (T1AB instruction)
Clear Interrupt Request
Timer 1 interrupt activated condition is cleared. Timer 1 interrupt request flag T1F "0" Timer 1 interrupt activated condition cleared (SNZT1 instruction)
Note when the interrupt request is cleared
When is executed, considering the skip of the next instruction according to the interrupt request flag T1F, insert the NOP instruction after the SNZT1 instruction.
Start Timer 1 Operation
Timer 1 and prescaler temporarily stopped are restarted.
b3 b0
Timer control register W1 1 0 1 0
Timer 1 operation start (TW1A instruction) Prescaler operation start
Enable Interrupts
The timer 1 interrupt which is temporarily disabled is enabled. b3 b0 Timer 1 interrupt occurrence enabled Interrupt control register V1 1 (TV1A instruction) All interrupts enabled (EI instruction) Interrupt enable flag INTE "1"
Stop CNTR Output
P12/CNTR I/O port is set to CNTR input port, and it is set to the high-impedance state.
b3 b0
Timer control register W6 0 0 CNTR input pin set (TW6A instruction)
b3 b0
Output latch of port P12 1 Input mode is set. (OP1A instruction) "": it can be "0" or "1."
Fig. 2.3.4 CNTR output setting example
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-27
APPLICATION 4506 Group 2.3 Timers
Disable Interrupts
Timer 2 interrupt is temporarily disabled. Interrupt enable flag INTE "0"
b3 b0
All interrupts disabled (DI instruction) Timer 2 interrupt occurrence disabled (TV1A instruction)
Interrupt control register V1
0
Stop Timer Operation
Timer operation is temporarily stopped. Timer 2 count source is selected.
b3 b0
Timer control register W2
0 1 0
Timer 2 stop (TW2A instruction) CNTR input selected for count source
Set Timer Value
Timer 2 count time is set. Timer 2 reload register R2 "6316" Timer count value 99 set (T2AB instruction)
Set port P12
P12/CNTR I/O port is set to input port.
b3 b0
Output latch of port P12 1 Input mode is set. (OP1A instruction)
b3 b0
Timer control register W6 0 Port P12 (I/O) set (TW6A instruction)
Clear Interrupt Request
Timer 2 interrupt activated condition is cleared. Timer 2 interrupt request flag T2F "0" Timer 2 interrupt activated condition cleared (SNZT2 instruction)
Note when the interrupt request is cleared
When is executed, considering the skip of the next instruction according to the interrupt request flag T2F, insert the NOP instruction after the SNZT2 instruction.
Start Timer 2 Operation
Timer 2 temporarily stopped is restarted.
b3 b0
Timer control register W2 1 1 0 Timer 2 operation start (TW2A instruction)
Enable Interrupts
The timer 2 interrupt which is temporarily disabled is enabled. b3 b0 Timer 2 interrupt occurrence enabled Interrupt control register V1 1 (TV1A instruction) Interrupt enable flag INTE "1" All interrupts enabled (EI instruction)
"": it can be "0" or "1."
Fig. 2.3.5 CNTR input setting example However, specify the pulse width input to CNTR pin. Refer to section "2.3.4 Notes on use" for the timer external input period condition.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-28
APPLICATION 4506 Group 2.3 Timers
Disable Interrupts
Timer 1 interrupt and INT interrupt are temporarily disabled. Interrupt enable flag INTE "0"
b3 b0
All interrupts disabled (DI instruction) (TV1A instruction) INT interrupt occurrence disabled
Interrupt control register V1
0 0 Timer 1 interrupt occurrence disabled
Initialize valid waveform
INT pin is initialized. INT pin input disabled, Timer 1 control disabled.
b3 b0
Interrupt control register I1
0 0 Timer 1 control disalbed
INT pin input disabled (TI1A instruction)
Stop Timer Operation
Timer 1 and prescaler are temporarily stopped. Dividing ratio of prescaler is selected.
b3
Timer 1 stop (TW1A instruction) Timer control register W1 0 1 0 1 Prescaler stop Prescaler divided by 16 selected Count start synchronous circuit selected
b0
Set Port
P13/INT pin is set to INT input.
b3 b0
Port P13 output latch
1 Input mode is set (OP1A instruction)
Set Timer Value
Timer 1 count time is set. Timer 1 reload register R1 "5216" Timer count value 82 set (T1AB instruction)
Clear Interrupt Request
Timer 1 interrupt activated condition is cleared. Timer 1 interrupt request flag T1F "0" Timer 1 interrupt activated condition cleared (SNZT1 instruction)
Note when the interrupt request is cleared
When is executed, considering the skip of the next instruction according to the interrupt request flag T1F, insert the NOP instruction after the SNZT1 instruction.
Start Timer Operation
Timer 1 and prescaler temporarily stopped are restarted. b3 b0 Timer 1 operating (TW1A instruction) Timer control register W1 1 1 1 1 Prescaler operating
Continue to Figure 2.3.7 on the next page.
Fig. 2.3.6 Timer start by external input setting example (1)
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-29
APPLICATION 4506 Group 2.3 Timers
Continued from Figure 2.3.6 on the preceding page.
Set Valid Waveform
Valid waveform of INT pin is selected. INT pin input enabled, rising selected, Timer 1 control is enabled.
b3 b0
Interrupt control register I1 1 1 0 1
Rising edge detected (TI1A instruction)
Set Auto-stop circuit
Timer 1 count auto-stop is selected. Interrupt control register W2
b3 b0
1
Timer 1 count auto-stop selected (TW2A instruction)
Clear Interrupt Request
INT interrupt activated condition is cleared. External 0 interrupt request flag EXF0 "0" INT interrupt activated condition cleared (SNZ0 instruction)
Note when the interrupt request is cleared
When is executed, considering the skip of the next instruction according to the interrupt request flag EXF0, insert the NOP instruction after the SNZ0 instruction.
11
Enable Interrupts
The timer 1 interrupt which is temporarily disabled is enabled. b3 b0 Timer 1 interrupt occurrence enabled Interrupt control register V1 1 (TV1A instruction) All interrupts enabled (EI instruction) Interrupt enable flag INTE "1"
"": it can be "0" or "1."
Timer start by external input
Fig. 2.3.7 Timer start by external input setting example (2)
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-30
APPLICATION 4506 Group 2.3 Timers
Main routine (every 20 ms) Reset Flag WDF1
Watchdog timer flag WDF1 is reset. "0" Watchdog timer flag WDF1 cleared (WRST instruction)
Note when the watchdog timer flag is cleared
When is executed, considering the skip of the next instruction according to the watchdog timer flag WDF1, insert the NOP instruction after the WRST instruction.
Main routine execution
Repeat
Do not clear watchdog timer flag WDF1 in interrupt service routine. Interrupt may be executed even if program run-away occurs.
When going to RAM back-up mode
* * * * * *
WRST NOP DI EPOF POF2
; WDF flag cleared ; Interrupt disabled ; POF2 instruction enabled
Oscillation stop (RAM back-up mode)
In the RAM back-up mode, WEF, WDF1 and WDF2 flags are initialized. However, when WDF2 flag is set to "1", at the same time, system enters RAM back-up mode, microcomputer may be reset. When watchdog timer and RAM back-up mode are used, execute the WRST instruction before system enters the RAM back-up mode to initialize WDF1 flag.
Fig. 2.3.8 Watchdog timer setting example 2.3.4 Notes on use (1) Prescaler Stop the prescaler operation to change its frequency dividing ratio. (2) Count source Stop timer 1 or 2 counting to change its count source. (3) Reading the count values Stop timer 1 or 2 counting and then execute the TAB1 or TAB2 instruction to read its data.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-31
APPLICATION 4506 Group 2.3 Timers
(4) Writing to the timer Stop timer 1 or 2 counting and then execute the T1AB or T2AB instruction to write its data. (5) Writing to reload register R1 When writing data to reload register R1 while timer 1 is operating, avoid a timing when timer 1 underflow. (6) Timer 1 and timer 2 count start timing and count time when operation starts Count starts from the first rising edge of the count source (2) after timer 1 and timer 2 operations start (1). Time to first underflow (3) is shorter (for up to 1 period of the count source) than time among next underflow (4) by the timing to start the timer and count source operations after count starts. When selecting CNTR input as the count source of timer 2, timer 2 operates synchronizing with the falling edge of CNTR input.
(2) Count Source Count Source (CNTR input) Timer Value 3 2 1 0 3 2 1 0 3 2
Timer Underflow Signal (3) (1) Timer (4)
Fig. 2.3.9
Timer count start timing and count time when operation starts (T1, T2)
(7) Watchdog timer * The watchdog timer function is valid after system is released from reset. When not using the watchdog timer function, execute the DWDT instruction and the WRST instruction continuously, and clear the WEF flag to "0" to stop the watchdog timer function. * The watchdog timer function is valid after system is returned from the RAM back-up. When not using the watchdog timer function, execute the DWDT instruction and the WRST instruction continuously every system is returned from the RAM back-up, and stop the watchdog timer function. (8) Pulse width input to CNTR pin Table 2.3.5 shows the recommended operating condition of pulse width input to CNTR pin. Table 2.3.5 Recommended operating condition of pulse width input to CNTR pin Parameter Timer external input period ("H" and "L" pulse width) Condition High-speed mode Middle-speed mode Low-speed mode Default mode Min. 3/f(XIN) 6/f(XIN) 12/f(XIN) 24/f(XIN) s Rating value Typ. Max. Unit
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-32
APPLICATION 4506 Group 2.4 A/D converter
2.4 A/D converter
The 4506 Group has a 2-channel A/D converter with the 10-bit successive comparison method. This A/D converter can also be used as a comparator to compare analog voltages input from the analog input pin with preset values. This section describes the related registers, application examples using the A/D converter and notes. Figure 2.4.1 shows the A/D converter block diagram.
Register B (4)
Register A (4) 4 IAP2 (P20, P21) OP2A (P20, P21) TAQ1 TQ1A 2
Q13 Q12 Q11 Q10
4 4
4 8 TABAD
8 TADAB
TALA Instruction clock 1/6
2 Q13
0
A/D control circuit
2-channel multi-plexed analog switch
1
ADF (1)
A/D interrupt
P20/AIN0 P21/AIN1
1
Comparator
0
Successive comparison register (AD) (10) 10 10
1
Q13 8
0 1
Q13
DAC operation signal
0
1
Q13
DAC DA converter
(Note 1)
8 8 VDD 8
VSS Comparator register (8)
(Note 2)
Notes 1: This switch is turned ON only when A/D converter is operating and generates the comparison voltage. 2: Writing/reading data to the comparator register is possible only in the comparator mode (Q13=1). The value of the comparator register is retained even when the mode is switched to the A/D conversion mode (Q13=0) because it is separated from the successive comparison register (AD). Also, the resolution in the comparator mode is 8 bits because the comparator register consists of 8 bits.
Fig. 2.4.1 A/D converter structure
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-33
APPLICATION 4506 Group 2.4 A/D converter
2.4.1 Related registers (1) A/D control register Q1 A/D operation mode control bit and analog input pin selection bits are assigned to register Q1. Set the contents of this register through register A with the TQ1A instruction. The TAQ1 instruction can be used to transfer the contents of register Q1 to register A. Table 2.4.1 shows the A/D control register Q1. Table 2.4.1 A/D control register Q1 A/D control register Q1 Q13 Q12 Q11 Analog input pin selection bits Q10 A/D operation mode control bit Not used at reset : 00002 0 1 0 1 Q11 Q10 0 0 1 0 1 0 at RAM back-up : state retained R/W
A/D conversion mode Comparator mode This bit has no function, but read/write is enabled. Selected pins AIN0 AIN1 Not available
1 1 Not available Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: When A/D converter is used, Q12 is not used. 2.4.2 A/D converter application examples (1) A/D conversion mode Outline: Analog input signal from a sensor can be converted into digital values. Specifications: Analog voltage values from a sensor is converted into digital values by using a 10bit successive comparison method. Use the AIN0 pin for this analog input. Figure 2.4.2 shows the A/D conversion mode setting example.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-34
APPLICATION 4506 Group 2.4 A/D converter
Disable Interrupts
A/D interrupt is temporarily disabled. All interrupts disabled (DI instruction) A/D interrupt occurrence disabled Interrupt control register V2 0 (TV2A instruction)
b3 b0
Interrupt enable flag INTE "0"
Set A/D Converter
A/D conversion mode is selected to A/D operation mode. Analog input pin AIN0 is selected.
b3 b0
A/D control register Q1 0 0 0 A/D conversion mode, AIN0 selected (TQ1A instruction)
Clear Interrupt Request
A/D interrupt activated condition is cleared. A/D conversion completion flag ADF "0" A/D conversion interrupt activated condition cleared (SNZAD instruction)
Note when the interrupt request is cleared
When is executed, considering the skip of the next instruction according to the flag ADF, insert the NOP instruction after the SNZAD instruction.
When interrupt is not used
When interrupt is used
Set Interrupt
Interrupts except A/D conversion is enabled (EI instruction)
Set Interrupt
A/D conversion interrupt temporarily disabled is enabled. Interrupt control register V2 1 A/D interrupt occurrence enabled (TV2A instruction) Interrupt enable flag INTE "1" All interrupts enabled (EI instruction)
b3 b0
Start A/D Conversion
A/D conversion operation is started (ADST instruction).
When interrupt is not used
When interrupt is used
Check A/D Interrupt Request
A/D conversion completion flag is checked (SNZAD instruciton)
A/D Conversion Interrupt Occur
Execute A/D Conversion
High-order 8 bits of register AD Register A and register B (TABAD instruction) Low-order 2 bits of register AD High-order 2 bits of register A (TALA instruction) "0" is set to low-order 2 bits of register A
When A/D conversion is executed by the same channel, to is repeated. When A/D conversion is executed by the another channel, to is repeated. "": it can be "0" or "1."
Fig. 2.4.2 A/D conversion mode setting example
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-35
APPLICATION 4506 Group 2.4 A/D converter
2.4.3 Notes on use (1) Note when the A/D conversion starts again When the A/D conversion starts again with the ADST instruction during A/D conversion, the previous input data is invalidated and the A/D conversion starts again. (2) A/D converter-1 Each analog input pin is equipped with a capacitor which is used to compare the analog voltage. Accordingly, when the analog voltage is input from the circuit with high-impedance and, charge/ discharge noise is generated and the sufficient A/D accuracy may not be obtained. Therefore, reduce the impedance or, connect a capacitor (0.01 F to 1 F) to analog input pins. Figure 2.4.3 shows the analog input external circuit example-1. When the overvoltage applied to the A/D conversion circuit may occur, connect an external circuit in order to keep the voltage within the rated range as shown the Figure 2.4.4. In addition, test the application products sufficiently.
Sensor
AIN (Note)
About 1 k
Sensor
AIN
Note: Apply the voltage within the specifications to an analog input pin.
Fig. 2.4.4 Analog input external circuit example-2
Fig. 2.4.3 Analog input external circuit example-1 (3) Notes for the use of A/D conversion 2 When the operating mode of the A/D converter is changed from the comparator mode to the A/D conversion mode with bit 3 of register Q1 in a program, be careful about the following notes. * Clear bit 2 of register V2 to "0" to change the operating mode of the A/D converter from the comparator mode to the A/D conversion mode with bit 3 of register Q1 (refer to Figure 2.4.5). * The A/D conversion completion flag (ADF) may be set when the operating mode of the A/D converter is changed from the comparator mode to the A/D conversion mode. Accordingly, set a value to bit 3 of register Q1, and execute the SNZAD instruction to clear the ADF flag. Do not change the operating mode (both A/D conversion mode and comparator mode) of A/D converter with bit 3 of register Q1 during operating the A/D converter. * * * Clear bit 2 of register V2 to "0"....... Change of the operating mode of the A/D converter from the comparator mode to the A/D conversion mode Clear the ADF flag to "0" with the SNZAD instruction Execute the NOP instruction for the case when a skip is performed with the SNZAD instruction * * * Fig. 2.4.5 A/D converter operating mode program example
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-36
APPLICATION 4506 Group 2.4 A/D converter
(4) A/D converter is used at the comparator mode The analog input voltage is higher than the comparison voltage as a result of comparison, the contents of ADF flag retains "0," not set to "1." In this case, the A/D interrupt does not occur even when the usage of the A/D interrupt is enabled. Accordingly, consider the time until the comparator operation is completed, and examine the state of ADF flag by software. The comparator operation is completed after 8 machine cycles. (5) Analog input pins Even when P20/AIN0 and P21/AIN1 are set to pins for analog input, they continue to function as P2 I/O. Accordingly, when any of them are used as these ports and others are used as analog input pins, make sure to set the outputs of pins that are set for analog input to "1." Also, the port input function of the pin functions as an analog input is undefined. (6) TALA instruction When the TALA instruction is executed, the low-order 2 bits of register AD is transferred to the highorder 2 bits of register A, and simultaneously, the low-order 2 bits of register A is "0." (7) Recommended operating conditions when using A/D converter The recommended operating conditions of supply voltage and system clock frequency when using A/ D converter are different from those when not using A/D converter. Table 2.4.2 shows the recommended operating conditions when using A/D converter. Table 2.4.2 Recommended operating conditions (when using A/D converter) Parameter Condition Limits Unit Min. Typ. Max. 0.1 4.4 0.1 2.2 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 Duty 40 % to 60 % 0.1 0.1 1.1 0.5 4.4 2.2 1.1 0.5 3.2 1.6 0.8 0.4 MHz
System clock frequency VDD = 2.7 to 5.5 V (high-speed mode) (at ceramic resonance) VDD = 2.7 to 5.5 V (middle-speed mode) VDD = 2.7 to 5.5 V (low-speed mode) VDD = 2.7 to 5.5 V (default mode) System clock frequency VDD = 2.7 to 5.5 V (high-speed mode) (at RC oscillation) (Note) VDD = 2.7 to 5.5 V (middle-speed mode) VDD = 2.7 to 5.5 V (low-speed mode) VDD = 2.7 System clock frequency VDD = 2.7 ( c e r a m i c r e s o n a n c e VDD = 2.7 selected, at external VDD = 2.7 clock input) VDD = 2.7 to 5.5 V (default mode) to 5.5 V (high-speed mode) to 5.5 V (middle-speed mode) to 5.5 V (low-speed mode) to 5.5 V (default mode)
Note: The frequency at RC oscillation is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-37
APPLICATION 4506 Group 2.5 Reset
2.5 Reset
System reset is performed by applying "L" level to the RESET pin for 1 machine cycle or more when the following conditions are satisfied: q the value of supply voltage is the minimum value or more of the recommended operating conditions q oscillation is stabilized. Then when "H" level is applied to RESET pin, the software starts from address 0 in page 0 after elapsing of the internal oscillation stabilizing time (On-chip oscillator (internal oscillator) clock is counted for 5359 times). Figure 2.5.2 shows the oscillation stabilizing time. 2.5.1 Reset circuit (1) Power-on reset Reset can be performed automatically at power on (power-on re-set) by connecting a diode and a capacitor to RESET pin. Connect RESET pin and the external circuit at the shortest distance.
VDD
VDD RESET pin voltage
Pull-up transistor Internal reset signal Watchdog timer output
(Note 1)
RESET
pin
(Note 2)
Reset state Internal reset signal
WEF
Reset released Power-on Notes 1: This symbol represents a parasitic diode. 2: Applied potential to RESET pin must be VDD or less.
Fig. 2.5.1 Structure of reset pin and its peripherals, and power-on reset operation
Reset input
=
On-chip oscillator (internal oscillator) is
1 machine cycle or more
counted 5359 times.
0.85VDD RESET 0.3VDD
Program starts (address 0 in page 0)
(Note)
Note: Keep the value of supply voltage to the minimum value or more of the recommended operating conditions.
Fig. 2.5.2 Oscillation stabilizing time after system is released from reset
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-38
APPLICATION 4506 Group 2.5 Reset
2.5.2 Internal state at reset Figure 2.5.3 shows the internal state at reset. The contents of timers, registers, flags and RAM other than shown in Figure 2.5.3 are undefined, so that set them to initial values.
* Program counter (PC) ............................................................................................ 000000 Address 0 in page 0 is set to program counter. 0 * Interrupt enable flag (INTE) ................................................................................... 0 * Power down flag (P) ............................................................................................... * External 0 interrupt request flag (EXF0) ................................................................ 0 0000 * Interrupt control register V1 ................................................................................... 0000 * Interrupt control register V2 ................................................................................... * Interrupt control register I1 .................................................................................... 0000 0 * Timer 1 interrupt request flag (T1F) ...................................................................... 0 * Timer 2 interrupt request flag (T2F) ...................................................................... * A/D conversion completion flag ADF ..................................................................... 0 0 * Watchdog timer flags (WDF1, WDF2) ................................................................... 1 * Watchdog timer enable flag (WEF) ....................................................................... * Timer control register W1 ...................................................................................... 0000 0000 * Timer control register W2 ...................................................................................... 0000 * Timer control register W6 ...................................................................................... * Clock control register MR ...................................................................................... 1100 0000 * Key-on wakeup control register K0 ....................................................................... 0000 * Key-on wakeup control register K1 ....................................................................... * Key-on wakeup control register K2 ....................................................................... 0000 0000 * Pull-up control register PU0 ................................................................................... 0000 * Pull-up control register PU1 ................................................................................... * Pull-up control register PU2 ................................................................................... 0000 0000 * A/D control register Q1 .......................................................................................... 0 * Carry flag (CY) ....................................................................................................... * Register A .............................................................................................................. 0000 0000 * Register B .............................................................................................................. * Register D .............................................................................................................. * Register E .............................................................................................................. 0000 * Register X .............................................................................................................. 0000 * Register Y .............................................................................................................. * Register Z ............................................................................................................... 111 * Stack pointer (SP) .................................................................................................. * Operation source clock ................................. On-chip oscillator (operation state) * Ceramic resonator ........................................................................ Operation state * RC oscillation circuit ............................................................................. Stop state "" represents undefined. (Prescaler, timer 1 stopped) (Timer 2 stopped) (Interrupt disabled) (Interrupt disabled) 0 0 0 0 0 0 0 0
(Interrupt disabled)
Fig. 2.5.3 Internal state at reset 2.5.3 Notes on use (1) Register initial value The initial value of the following registers are undefined after system is released from reset. After system is released from reset, set initial values. * Register Z (2 bits) * Register D (3 bits) * Register E (8 bits)
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-39
APPLICATION 4506 Group 2.6 RAM back-up
2.6 RAM back-up
2.6.1 RAM back-up mode The system enters RAM back-up mode when the POF2 instruction is executed after the EPOF instruction is executed. Table 2.6.1 shows the function and state retained at RAM back-up mode. Also, Table 2.6.2 shows the return source from this state. (1) RAM back-up mode As oscillation stops with RAM, the state of reset circuit retained, current dissipation can be reduced without losing the contents of RAM. Table 2.6.1 Functions and states retained at RAM back-up mode Function Program counter (PC), registers A, B, carry flag (CY), stack pointer (SP) (Note 2) Contents of RAM Port level Selected oscillation circuit Timer control register W1 Timer control registers W2, W6 Clock control register MR Interrupt control registers V1, V2 Interrupt control register I1 Timer 1 function Timer 2 function A/D function Pull-up control registers PU0-PU2 Key-on wakeup control registers K0-K2 A/D control register Q1 External 0 interrupt request flag (EXF0) Timer 1 interrupt request flag (T1F) Timer 2 interrupt request flag (T2F) A/D conversion completion flag (ADF) Watchdog timer flag (WDF1) Watchdog timer enable flag (WEF) 16-bit timer (WDT) Interrupt enable flag (INTE) RAM back-up POF2 O (Note 5) O O O (Note 3) O O O (Note 3) (Note 4) (Note 4)
Notes 1: "O" represents that the function can be retained, and "" represents that the function is initialized. Registers and flags other than the above are undefined at RAM back-up, and set an initial value after returning. 2: The stack pointer (SP) points the level of the stack register and is initialized to "7" at RAM back-up. 3: The state of the timer flag WDF1 is undefined. 4: Initialize the watchdog timer flag WDF1 with the WRST instruction, and then execute the POF2 instruction. 5: As for the D2/C pin, the output latch of port C is set to "1" at the RAM back-up. However, the output latch of port D2 is retained. As for the other ports, their output levels are retained at the RAM back-up.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-40
APPLICATION 4506 Group 2.6 RAM back-up
Table 2.6.2 Return source and return condition Return source Return condition Remarks Return by an external "L" level input. Key-on wakeup function can be selected with Port P0 every one port. Set the port using the key-on Port P1 (Note) wakeup function to "H" level before going into Port P2 the RAM back-up state. Port D2/C Port D3/K Return by an external "H" level or "L" Select the return level ("L" level or "H" level) Port P13/INT level input. The return level can be with the bit 2 of register I1 according to the (Note) selected by register I12. When the external state before going into the RAM backreturn level is input, the EXF0 flag is up state.
not set. Note: When the bit 3 (K13) of the key-on wakeup control register K1 is "0", the key-on wakeup ("H" level or "L" level) of INT pin is set. When the K13 is "1", the key-on wakeup ("L" level) of port P13 is set. (2) Start condition identification When system returns from both RAM back-up mode and reset, software is started from address 0 in page 0. The start condition (warm start or cold start) can be identified by examining the state of the power down flag (P) with the SNZP instruction. Table 2.6.3 Start condition identification Return condition External wakeup signal input Reset P flag 1 0
Program start P = "1" ? No Cold start Yes
External wakeup signal
Warm start
Fig. 2.6.1 Start condition identified example
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-41
APPLICATION 4506 Group 2.6 RAM back-up
2.6.2 Related registers (1) Key-on wakeup control register K0 Register K0 controls the ON/OFF of the key-on wakeup function of ports P00-P03. Set the contents of this register through register A with the TK0A instruction. The contents of register K0 is transferred to register A with the TAK0 instruction. Table 2.6.4 shows the key-on wakeup control register K0. Table 2.6.4 Key-on wakeup control register K0 Key-on wakeup control register K0 K03 K02 K01 K00 Port P03 key-on wakeup control bit Port P02 key-on wakeup control bit Port P01 key-on wakeup control bit Port P00 key-on wakeup control bit at reset : 00002 0 1 0 1 0 1 0 1 at RAM back-up : state retained R/W
Key-on wakeup invalid Key-on wakeup valid Key-on wakeup invalid Key-on wakeup valid Key-on wakeup invalid Key-on wakeup valid Key-on wakeup invalid Key-on wakeup valid
Note: "R" represents read enabled, and "W" represents write enabled. (2) Key-on wakeup control register K1 Register K1 controls the ON/OFF of the key-on wakeup function of ports P10-P13. Set the contents of this register through register A with the TK1A instruction. The contents of register K1 is transferred to register A with the TAK1 instruction. Table 2.6.5 shows the key-on wakeup control register K1. Table 2.6.5 Key-on wakeup control register K1 Key-on wakeup control register K1 K13 K12 K11 K10 Port P13/INT key-on wakeup control bit Port P12/CNTR key-on wakeup control bit Port P11 key-on wakeup control bit Port P10 at reset : 00002 0 1 0 1 0 1 0 at RAM back-up : state retained R/W
P13 key-on wakeup invalid/INT pin key-on wakeup valid P13 key-on wakeup valid/INT pin key-on wakeup invalid Key-on wakeup invalid Key-on wakeup valid Key-on wakeup invalid Key-on wakeup valid Key-on wakeup invalid
key-on wakeup control bit Key-on wakeup valid 1 Note: "R" represents read enabled, and "W" represents write enabled.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-42
APPLICATION 4506 Group 2.6 RAM back-up
(3) Key-on wakeup control register K2 Register K2 controls the ON/OFF of the key-on wakeup function of ports P20, P21, D2/C and D3/K. Set the contents of this register through register A with the TK2A instruction. The contents of register K2 is transferred to register A with the TAK2 instruction. Table 2.6.6 shows the key-on wakeup control register K2. Table 2.6.6 Key-on wakeup control register K2 Key-on wakeup control register K2 K23 K22 K21 K20 Port D3/K key-on wakeup control bit Port D2/C key-on wakeup control bit Port P21/AIN1 key-on wakeup control bit Port P20/AIN0 key-on wakeup control bit at reset : 00002 0 1 0 1 0 1 0 at RAM back-up : state retained R/W
Key-on wakeup invalid Key-on wakeup valid Key-on wakeup invalid Key-on wakeup valid Key-on wakeup invalid Key-on wakeup valid Key-on wakeup invalid
Key-on wakeup valid 1 Note: "R" represents read enabled, and "W" represents write enabled.
(4) Pull-up control register PU0 Register PU0 controls the ON/OFF of the ports P00-P03 pull-up transistor. Set the contents of this register through register A with the TPU0A instruction. Table 2.6.7 shows the pull-up control register PU0. Table 2.6.7 Pull-up control register PU0 Pull-up control register PU0 PU03 PU02 PU01 PU00 Port P03 pull-up transistor control bit Port P02 pull-up transistor control bit Port P01 pull-up transistor control bit Port P00 at reset : 00002 0 1 0 1 0 1 0 1 at RAM back-up : state retained W
Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON
pull-up transistor control bit Note: "W" represents write enabled.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-43
APPLICATION 4506 Group 2.6 RAM back-up
(5) Pull-up control register PU1 Register PU1 controls the ON/OFF of the ports P10-P13 pull-up transistor. Set the contents of this register through register A with the TPU1A instruction. Table 2.6.8 shows the pull-up control register PU1. Table 2.6.8 Pull-up control register PU1 Pull-up control register PU1 PU13 PU12 PU11 PU10 Port P13/INT pull-up transistor control bit Port P12/CNTR pull-up transistor control bit Port P11 pull-up transistor control bit Port P10 at reset : 00002 0 1 0 1 0 1 0 1 at RAM back-up : state retained W
Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON
pull-up transistor control bit Note: "W" represents write enabled.
(6) Pull-up control register PU2 Register PU2 controls the ON/OFF of the ports P20, P21, D2/C and D3/K pull-up transistor. Set the contents of this register through register A with the TPU2A instruction. Table 2.6.9 shows the pull-up control register PU2. Table 2.6.9 Pull-up control register PU2 Pull-up control register PU2 PU23 PU22 PU21 PU20 Port D3/K pull-up transistor control bit Port D2/C pull-up transistor control bit Port P21/AIN1 pull-up transistor control bit Port P20/AIN0 at reset : 00002 0 1 0 1 0 1 0 1 at RAM back-up : state retained W
Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON
pull-up transistor control bit Note: "W" represents write enabled.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-44
APPLICATION 4506 Group 2.6 RAM back-up
(7) Interrupt control register I1 The INT pin timer 1 control enable bit is assigned to bit 0, INT pin edge detection circuit control bit is assigned to bit 1, interrupt valid waveform for INT pin/return level selection bit is assigned to bit 2 and INT pin input control bit is assigned to bit 3. Set the contents of this register through register A with the TI1A instruction. In addition, the TAI1 instruction can be used to transfer the contents of register I1 to register A. Table 2.6.10 shows the interrupt control register I1. Table 2.6.10 Interrupt control register I1 Interrupt control register I1 I13 INT pin input control bit (Note 2) Interrupt valid waveform for INT pin/return level selection bit (Note 2) INT pin edge detection circuit control bit INT pin at reset : 00002 0 1 0 1 0 1 at RAM back-up : state retained R/W
INT pin input disabled INT pin input enabled Falling waveform ("L" level of INT pin is recognized with the SNZI0 instruction)/"L" level Rising waveform ("H" level of INT pin is recognized with the SNZI0 instruction)/"H" level One-sided edge detected Both edges detected
I12
I11 I10
Disabled 0 Enabled timer 1 control enable bit 1 Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set. Accordingly, after the one instruction is executed, clear EXF0 flag with the SNZ0 instruction while the bit 0 (V10) of register V1 is "0". In this time, set the NOP instruction after the SNZ0 instruction, for the case when a skip is performed with the SNZ0 instruction.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-45
APPLICATION 4506 Group 2.6 RAM back-up
2.6.3 Notes on use (1) Key-on wakeup function After setting ports (P0, P1, D2/C, D3/K, P20/AIN0 and P21/AIN1 specified with register K0-K2) which key-on wakeup function is valid to "H," execute the POF2 instruction. If one of ports which key-on wakeup function is valid is in the "L" level state, system returns from the RAM back-up after the POF2 instruction is executed. (2) POF2 instruction Execute the POF2 instruction immediately after executing the EPOF instruction to enter the RAM back-up state. Note that system cannot enter the RAM back-up state when executing only the POF2 instruction. Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction and the POF2 instruction. (3) Return from RAM back-up After system returns from RAM back-up, set the undefined registers and flags. The initial value of the following registers are undefined at RAM back-up. After system is returned from RAM back-up, set initial values. * Register Z (2 bits) * Register X (4 bits) * Register Y (4 bits) * Register D (3 bits) * Register E (8 bits) (4) Watchdog timer The watchdog timer function is valid after system is returned from the RAM back-up. When not using the watchdog timer function, execute the DWDT instruction and the WRST instruction continuously every system is returned from the RAM back-up, and stop the watchdog timer function. (5) P13/INT pin When the bit 3 of register I1 is cleared, the RAM back-up mode is selected and the input of INT pin is disabled, be careful about the following notes. * When the key-on wakeup function of port P13 is not used (register K13 = "0"), clear bits 2 and 3 of register I1 before system enters to the RAM back-up mode. (6) External clock When the external signal clock is used as the source oscillation (f(XIN)), note that the RAM backup mode (POF2 instruction) cannot be used.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-46
APPLICATION 4506 Group 2.7 Oscillation circuit
2.7 Oscillation circuit
The 4506 Group has an internal oscillation circuit to produce the clock required for microcomputer operation. The ceramic resonance and the RC oscillation can be used for the source clock. After system is released from reset, the 4506 Group starts operation by the clock output from the on-chip oscillator which is the internal oscillator. 2.7.1 Oscillation circuit (1) f(XIN) clock generating circuit The ceramic resonator or RC oscillation can be used for the source oscillation (f(XIN)) of the MCU. After system is released from reset, the 4506 Group starts operation by the clock output from the on-chip oscillator which is the internal oscillator. When the ceramic resonator is used, execute the CMCK instruction. When the RC oscillation is used, execute the CRCK instruction. The oscillation circuit by the CMCK or CRCK instruction can be selected only at once. The oscillation circuit corresponding to the first executed one of these two instructions is valid. Other oscillation circuit and the on-chip oscillator stop. Execute the CMCK or the CRCK instruction in the initial setting routine of program (executing it in address 0 in page 0 is recommended). Also, when the CMCK or the CRCK instruction is not executed in program, the 4506 Group operates by the on-chip oscillator. (2) On-chip oscillator operation When the MCU operates by the on-chip oscillator as the source oscillation (f(XIN)) without using the ceramic resonator or the RC oscillator, connect XIN pin to VSS and leave XOUT pin open (Figure 2.7.2). The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that variable frequencies when designing application products.
Reset On-chip oscillator operation CMCK instruction CRCK instruction
* Ceramic resonator valid * RC oscillation valid * On-chip oscillator stop * On-chip oscillator stop * Ceramic resonator stop * RC oscillation stop
Fig. 2.7.1 Switch to ceramic resonance/RC oscillation
4506
o e he n uc n * DnodnCtRuCsK tinstrCMtCK iin sptrrogtriaom. a uc ion
XOUT
XIN
Fig. 2.7.2 Handling of XIN and XOUT when operating on-chip oscillator
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-47
APPLICATION 4506 Group 2.7 Oscillation circuit
(3) Ceramic resonator When the ceramic resonator is used as the source oscillation (f(XIN)), connect the ceramic resonator and the external circuit to pins XIN and XOUT at the shortest distance. Then, execute the CMCK instruction. A feedback resistor is built in between pins XIN and XOUT (Figure 2.7.3). As for the oscillation frequency, do not exceed the values shown in the Table 2.7.1.
Execute the CMCK instruction in program.
4506
XIN
XOUT
CIN
Note: Externally connect a damping resistor Rd depending on the oscillation frequency. (A feedback resistor is built-in.) Rd Use the resonator manufacturer's recommended value because constants such as COUT capacitance depend on the resonator.
Fig. 2.7.3 Ceramic resonator external circuit Table 2.7.1 Maximum value of oscillation frequency and supply voltage Supply voltage Oscillation frequency (System clock) 2.7 V to 5.5 V High-speed mode 4.4 MHz (f(XIN)) 2.0 V to 5.5 V (f(XIN)) High-speed mode 2.2 MHz 4.4 MHz (f(XIN)/2) Middle-speed mode (f(XIN)/4) Low-speed mode (f(XIN)/8) Default mode
(4) RC oscillation When the RC oscillation is used as the source oscillation (f(XIN)), connect the XIN pin to the external circuit of resistor R and the capacitor C at the shortest distance and leave XOUT pin open. Then, execute the CRCK instruction (Figure 2.7.4). The frequency is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits.
4506
R C
XIN
XOUT
* Execute the CRCK instruction in program.
Fig. 2.7.4 External RC oscillation circuit
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-48
APPLICATION 4506 Group 2.7 Oscillation circuit
2.7.2 Oscillation operation System clock is supplied to CPU and peripheral device as the standard clock for the microcomputer operation. For the 4506 Group, the clock supplied from the on-chip oscillator (internal oscillator) or the ceramic resonance circuit, RC oscillation circuit is selected from the high-speed mode (f(XIN)), middlespeed mode (f(XIN)/2), low-speed mode (f(XIN)/4) or default mode (f(XIN)/8) with the register MR. Figure 2.7.5 shows the structure of the clock control circuit.
Division circuit divided by 8 divided by 4
MR3, MR2 11 10 01 00
System clock Internal clock generation circuit (divided by 3)
On-chip oscillator (internal oscillator) (Note 1)
Instruction clock Counter
divided by 2
Multiplexer
QS QR
RC oscillation circuit
QS R XIN XOUT CRCK instruction
Wait time (Note 2) control circuit
Program start signal
Ceramic resonator circuit
QS R QS R CMCK instruction RESET pin
Key-on wakeup signal
EPOF instruction + (POF2 instruction)
Notes 1: System operates by the on-chip oscillator clock (f(RING)) until the CMCK or CRCK instruction is executed after system is released from reset. 2: The wait time control circuit is used to generate the time required to stabilize the f(XIN) oscillation. After the certain oscillation stabilizing wait time elapses, the program start signal is output. This circuit operates when system is released from reset or returned from RAM back-up.
Fig. 2.7.5 Structure of clock control circuit
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-49
APPLICATION 4506 Group 2.7 Oscillation circuit
2.7.3 Notes on use (1) Clock control Execute the CMCK or the CRCK instruction in the initial setting routine of program (executing it in address 0 in page 0 is recommended). The oscillation circuit by the CMCK or CRCK instruction can be selected only at once. The oscillation circuit corresponding to the first executed one of these two instructions is valid. Other oscillation circuits and the on-chip oscillator stop. (2) On-chip oscillator The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that variable frequencies when designing application products. Also, the oscillation stabilize wait time after system is released from reset is generated by the onchip oscillator clock. When considering the oscillation stabilize wait time after system is released from reset, be careful that the variable frequency of the on-chip oscillator clock. (3) External clock When the external signal clock is used as the source oscillation (f(XIN)), note that the RAM back-up mode (POF2 instruction) cannot be used. (4) Value of a part connected to an oscillator Values of a capacitor and a resistor of the oscillation circuit depend on the connected oscillator and the board. Accordingly, consult the oscillator manufacturer for values of each part connected the oscillator.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
2-50
CHAPTER 3 APPENDIX
3.1 3.2 3.3 3.4 3.5 Electrical characteristics Typical characteristics List of precautions Notes on noise Package outline
APPENDIX 4506 Group 3.1 Electrical characteristics
3.1 Electrical characteristics
3.1.1 Absolute maximum ratings Table 3.1.1 Absolute maximum ratings
Symbol VDD VI VI VO VO Pd Topr Tstg Parameter Supply voltage Input voltage P0, P1, P2, D0, D1, D2/C, D3/K,
RESET, XIN
Conditions
Ratings -0.3 to 6.5 -0.3 to VDD+0.3 -0.3 to VDD+0.3
Unit V V V V V mW C C
Input voltage AIN0-AIN1 Output voltage P0, P1, P2, D0, D1, D2/C, D3/K,
RESET
Output transistors in cut-off state
-0.3 to VDD+0.3 -0.3 to VDD+0.3 300 -20 to 85 -40 to 125
Output voltage XOUT Power dissipation Operating temperature range Storage temperature range Ta = 25 C
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-2
APPENDIX 4506 Group 3.1 Electrical characteristics
3.1.2 Recommended operating conditions Table 3.1.2 Recommended operating conditions 1
(Ta = -20 C to 85 C, VDD = 2.0 to 5.5 V, unless otherwise noted) Symbol VDD Parameter Supply voltage (with a ceramic resonator) Conditions High-speed mode Middle-speed mode Low-speed mode VDD Supply voltage (with RC oscillation) Default mode High-speed mode Middle-speed mode Low-speed mode Default mode VRAM VSS VIH VIH VIH VIH VIL VIL VIL VIL IOL(peak) IOL(peak) IOL(peak) IOL(peak) IOL(avg) IOL(avg) IOL(avg) IOL(avg) IOL(avg) RAM back-up voltage Supply voltage "H" level input voltage "H" level input voltage "H" level input voltage "H" level input voltage "L" level input voltage "L" level input voltage "L" level input voltage "L" level input voltage "L" level peak output current "L" level peak output current "L" level peak output current "L" level peak output current "L" level average output current "L" level average output current "L" level average output current "L" level average output current "L" level total average current (at RAM back-up) P0, P1, P2, D0-D3, XIN
RESET
Limits Min. 2.7 2.0 Typ. Max. 5.5 5.5
Unit V
f(XIN) 4.4 MHz f(XIN) 4.4 MHz
f(XIN) 4.4 MHz
2.7
5.5
V
1.8 0 0.8VDD VDD = 4.0 to 5.5 V VDD = 2.0 to 5.5 V 0.85VDD 0.5VDD 0.7VDD 0.85VDD 0 0 0 0 VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD VDD VDD VDD VDD 0.2VDD 0.16VDD 0.3VDD 0.15VDD 10 4.0 40 30 24 12 24 12 5.0 2.0 30 15 15 7.0 12 6.0 80 80
V V V V V V V V V V mA mA mA mA mA mA mA mA mA
C, K CNTR, INT P0, P1, P2, D0-D3, XIN C, K
RESET
CNTR, INT P2, RESET D0, D1 D2/C, D3/K P0, P1 P2, RESET (Note) D0, D1 (Note) D2/C, D3/K (Note) P0, P1 (Note) P2, D, RESET P0, P1
Note : The average output current (IOH, IOL) is the average value during 100 ms.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-3
APPENDIX 4506 Group 3.1 Electrical characteristics
Ceramic resonator and high-speed mode selected f [MHz]
Except ceramic resonator and high-speed mode f [MHz]
4.4
4.4
Recommended operating condition 2.2
Recommended operating condition
2.0
2.7
5.5
VDD[V]
2.0
5.5
VDD[V]
RC oscillation circuit selected
f [MHz]
External clock input, high-speed mode selected (ceramic resonator selected) f [MHz]
4.4
3.2
Recommended operating condition 1.6
Recommended operating condition
2.7
5.5
VDD[V]
2.0
2.7
5.5
VDD[V]
Except external clock input, high-speed mode (ceramic resonator selected) f [MHz]
3.2 Recommended operating condition
2.0
5.5
VDD[V]
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-4
APPENDIX 4506 Group 3.1 Electrical characteristics
Table 3.1.3 Recommended operating conditions 2
(Ta = -20 C to 85 C, VDD = 2.0 to 5.5 V, unless otherwise noted) Symbol f(XIN) Parameter Oscillation frequency (with a ceramic resonator) High-speed mode Middle-speed mode Low-speed mode Default mode f(XIN) Oscillation frequency (with RC oscillation) (Note) High-speed mode Middle-speed mode Low-speed mode Default mode f(XIN) Oscillation frequency (with a ceramic resonator selected, external clock input) Middle-speed mode Low-speed mode Default mode f(XIN) Oscillation frequency error (at RC oscillation, error value of exteranal R, C not included) Note: use 30 pF capacitor and vary external R f(CNTR) Timer external input frequency High-speed mode Middle-speed mode Low-speed mode tw(CNTR) Timer external input period ("H" and "L" pulse width) Default mode High-speed mode Middle-speed mode Low-speed mode Default mode 3/f(XIN) 6/f(XIN) 12/f(XIN) 24/f(XIN) f(XIN)/6 f(XIN)/12 f(XIN)/24 f(XIN)/48 s Hz VDD = 3.0 V 10 %, Ta = 25 C, -20 to 85 C 17 VDD = 5.0 V 10 %, Ta = 25 C, -20 to 85 C 17 High-speed mode VDD = 2.7 V to 5.5 V VDD = 2.0 V to 5.5 V VDD = 2.0 V to 5.5 V 3.2 1.6 3.2 MHz VDD = 2.7 V to 5.5 V 4.4 MHz Conditions VDD = 2.7 V to 5.5 V VDD = 2.0 V to 5.5 V VDD = 2.0 V to 5.5 V Limits Typ. Max. 4.4 2.2 4.4 Unit MHz
Min.
%
Note: The frequency at RC oscillation is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-5
APPENDIX 4506 Group 3.1 Electrical characteristics
3.1.3 Electrical characteristics Table 3.1.4 Electrical characteristics
Symbol VOL Parameter "L" level output voltage P0, P1 VDD = 3.0 V VOL "L" level output voltage P2, RESET VDD = 3.0 V VOL "L" level output voltage D0, D1 VDD = 3.0 V VOL "L" level output voltage D2/C, D3/K VDD = 3.0 V IIH IIH IIL IIL IDD "H" level input current P0, P1, P2, RESET "H" level input current D0, D1, D2/C, D3/K "L" level input current P0, P1, P2 "L" level input current D0, D1, D2/C, D3/K Supply current at active mode (Note 1) VI = 0 V, D2/C, D3/K, No pull-up VDD = 5.0 V f(XIN) = 4.0 MHz High-speed mode Middle-speed mode Low-speed mode Default mode VDD = 3.0 V f(XIN) = 2.0 MHz High-speed mode Middle-speed mode Low-speed mode Default mode at RAM back-up mode Ta = 25 C VDD = 3.0 V RPU Pull-up resistor value P0, P1, P2, D2/C, D3/K, RESET VT+ - VT- Hysteresis INT, CNTR VT+ - VT- Hysteresis RESET f(RING) On-chip oscillator clock frequency (Note 2) VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V 1.0 0.5 VI = 0 V VDD = 5.0 V VDD = 3.0 V 30 50 60 120 0.25 0.25 1.2 0.5 2.0 1.0 3.0 1.8 V MHz (POF2 instruction execution) VDD = 5.0 V -1.0 1.7 1.3 1.1 1.0 0.5 0.4 0.35 0.3 0.1 5.0 3.9 3.3 3.0 1.5 1.2 1.1 0.9 1.0 10 6.0 150 300 V k VI = 0 V P0, P1, P2 No pull-up -1.0 VI = VDD VI = VDD VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V VDD = 5.0 V (Ta = -20 C to 85 C, VDD = 2.0 to 5.5 V, unless otherwise noted) Test conditions IOL = 12 mA IOL = 4.0 mA IOL = 6.0 mA IOL = 2.0 mA IOL = 5.0 mA IOL = 1.0 mA IOL = 2.0 mA IOL = 30 mA IOL = 10 mA IOL = 15 mA IOL = 5.0 mA IOL = 15 mA IOL = 5.0 mA IOL = 9.0 mA IOL = 3.0 mA Limits Min. Typ. Max. 2.0 0.9 0.9 0.6 2.0 0.6 0.9 2.0 0.9 2.0 0.9 2.0 0.9 2.0 0.9 1.0 1.0 V V V Unit V
A A A A
mA
A
Notes 1: When the A/D converter is used, the A/D operation current (IADD) is included. 2: When system operates by the on-chip oscillator, the system clock frequency is the on-chip oscillator clock divided by the dividing ratio selected with register MR.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-6
APPENDIX 4506 Group 3.1 Electrical characteristics
3.1.4 A/D converter recommended operating conditions Table 3.1.5 A/D converter recommended operating conditions
(Comparator mode included, Ta = -20 C to 85 C, unless otherwise noted) Symbol VDD VIA f(XIN) Parameter Supply voltage Analog input voltage Oscillation frequency VDD = 2.7 V to 5.5 V High-speed mode Middle-speed mode Low-speed mode Default mode Ta = 25 C Ta = -20 C to 85 C Conditions Min. 2.7 3.0 0 0.1 0.2 0.4 0.8 Limits Typ. Max. 5.5 5.5 VDD+2LSB V MHz Unit V
Table 3.1.6 A/D converter characteristcs
(Comparator mode included, Ta = -20 C to 85 C, unless otherwise noted) Symbol - - - V0T VFST IADD TCONV Parameter Resolution Linearity error Differential non-linearity error Zero transition voltage Full-scale transition voltage A/D operating current (Note 1) A/D conversion time Ta = 25 C, VDD = 2.7 V to 5.5 V Ta = -25 C to 85 C, VDD = 3.0 V to 5.5 V Ta = 25 C, VDD = 2.7 V to 5.5 V Ta = -25 C to 85 C, VDD = 3.0 V to 5.5 V VDD = 5.12 V VDD = 3.072 V VDD = 5.12 V VDD = 3.072 V VDD = 5.0 V VDD = 3.0 V f(XIN) = 4.0 MHz High-speed mode Middle-speed mode Low-speed mode Default mode - - - Comparator resolution Comparator error (Note 2) Comparator comparison time VDD = 5.12 V VDD = 3.072 V f(XIN) = 4.0 MHz High-speed mode Middle-speed mode Low-speed mode Default mode 10 3 5115 3063 20 9 5125 3069 0.3 0.1 0.9 30 15 5135 3075 0.9 0.3 46.5 93.0 186 372 8 20 15 6.0 12 24 48 bits mV mV mA LSB mV Test conditions Min. Limits Typ. Max. 10 2.0 Unit bits LSB
s
s
Notes 1: When the A/D converter is used, the IADD is included to IDD. 2: As for the error from the logic value in the comparator mode, when the contents of the comparator register is n, the logic value of the comparison voltage Vref which is generated by the built-in DA converter can be obtained by the following formula.
Logic value of comparison voltage Vref Vref = VDD 256 n
n = Value of register AD (n = 0 to 255)
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-7
APPENDIX 4506 Group 3.1 Electrical characteristics
3.1.5 Basic timing diagram
Machine cycle
Parameter Clock
Pin name
Mi
Mi+1
XIN : high-speed mode
(System clock = f(XIN))
XIN : middle-speed mode
(System clock = f(XIN)/2)
XIN : low-speed mode
(System clock = f(XIN)/4)
XIN : default mode
(System clock = f(XIN)/8)
Port D output
D0, D1, D2/C, D3/K
Port D input
D0, D1, D2/C, D3/K
Port P0, P1, P2 output
P00-P03 P10-P13 P20, P21 P00-P03 P10-P13 P20, P21
Port P0, P1, P2 input
Timer output Timer input
CNTR CNTR
Interrupt input
INT
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-8
APPENDIX 4506 Group 3.2 Typical characteristics
3.2 Typical characteristics
The data described below are characteristic examples for the 4506 Group. Unless otherwise noted, the characteristics for Mask ROM version are shown here. The data shown here are just characteristics examples and are not guaranteed. For rated values, refer to "3.1 Electrical characteristics". Standard characteristics are different between Mask ROM version and One Time PROM version, due to the difference in the manufacturing processes. Even in the MCUs which have the same memory type, standard characteristics are different in each sample, too. 3.2.1 VDD-IDD characteristics (1) VDD-IDD characteristics (Ta = 25 C, f(XIN) = 4 MHz, at ceramic resonance)
2.5
High-speed mode
2.0
Middle-speed mode
1.5
IDD [mA]
Low-speed mode Default mode
1.0
0.5
0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD [V] (2) VDD-IDD characteristics (Ta = 25 C, f(XIN) = 2 MHz, at ceramic resonance)
2.0
High-speed mode
1.5
IDD [mA]
Middle-speed mode Low-speed mode Default mode
1.0
0.5
0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD [V]
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-9
APPENDIX 4506 Group 3.2 Typical characteristics
(3) VDD-IDD characteristics (Ta = 25 C, f(XIN) = 1 MHz, at ceramic resonance)
2.0
1.5
High-speed mode Middle-speed mode Low-speed mode Default mode
1.0
IDD [mA]
0.5
0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD [V] (4) VDD-IDD characteristics (Ta = 25 C, f(XIN) = 400 kHz, at ceramic resonance)
2.0
1.5
IDD [mA]
1.0
High-speed mode Middle-speed mode Low-speed mode Default mode
0.5
0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD [V]
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-10
APPENDIX 4506 Group 3.2 Typical characteristics
(5) R-IDD characteristics (Ta = 25 C, at RC oscillation, VDD = 5 V, C = 33 pF)
2.5
High-speed mode
2.0
Middle-speed mode
1.5
Low-speed mode Default mode
IDD [mA]
1.0
0.5
0.0 0.0 5.0 10.0 15.0 20.0
Resistor R [k] (6) VDD-IDD characteristics (Ta = 25 C, on-chip oscillator)
1.0 0.9
High-speed mode
0.8 0.7 0.6
Middle-speed mode
IDD [mA]
0.5 0.4 0.3 0.2 0.1 0.0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Low-speed mode Default mode
VDD [V]
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-11
APPENDIX 4506 Group 3.2 Typical characteristics
(7) VDD-IDD characteristics (Ta = 25 C, at RAM back-up)
100
80
60
IDD [nA]
40
20
0
-20 1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD [V]
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-12
APPENDIX 4506 Group 3.2 Typical characteristics
3.2.2 Frequency characteristics (1) On-chip oscillator frequency VDD-f(RING) characteristics
4.0
3.5
3.0
Ta = -30 C Ta = 25 C
2.5
f(RING) [MHz]
2.0
Ta = 95 C
1.5
1.0
0.5
0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD [V] (2) On-chip oscillator frequency Ta-f(RING) characteristics
3.5
3.0
2.5
2.0
f(RING) [MHz]
1.5
VDD = 5.0 V
1.0
VDD = 3.0 V
0.5
0.0 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
Ta [C]
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-13
APPENDIX 4506 Group 3.2 Typical characteristics
(3) RC oscillation frequency (R-f(XIN)) characteristics (VDD = 5.0 V, Ta = 25 C, C = 33pF)
6.0
5.0
4.0
3.0
f(XIN) [MHz]
2.0
1.0
0.0 0.0 5.0 10.0 15.0 20.0
Resistor R [k] (4) RC oscillation frequency (Ta-f(XIN)) characteristics (VDD = 5.0 V, C = 33pF)
5.5 5.0
3.3 k
4.5 4.0 3.5 3.0 2.5 2.0 1.5
4.7 k
f(XIN)[MHz]
6.8 k 9.1 k 15 k
1.0 0.5 0.0 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
20 k
100
Ta [C]
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-14
APPENDIX 4506 Group 3.2 Typical characteristics
3.2.3 VOL-IOL characteristics (VDD = 5 V) (1) Ports P0, P1
Ta = -30 C
100 90 80
Ta = 25 C
Ta = 95 C
70 60
IOL [mA]
50 40 30 20 10 0 0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VOL [V] (2) Ports P2, RESET pin
100 90 80 70 60
IOL [mA]
Ta = -30 C
50 40 30 20 10 0 0.0
Ta = 25 C Ta = 95 C
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VOL [V]
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-15
APPENDIX 4506 Group 3.2 Typical characteristics
(3) Ports D0, D1
Ta = -30 C Ta = 25 C Ta = 95 C
100 90 80 70 60 50
IOL [mA]
40 30 20 10 0 0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VOL [V] (4) Ports D2/C, D3/K
100 90 80
70
Ta = -30 C
60
IOL [mA]
Ta = 25 C
50 40 30
Ta = 95 C
20 10 0 0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VOL [V]
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-16
APPENDIX 4506 Group 3.2 Typical characteristics
3.2.4 VOL-IOL characteristics (VDD = 3 V) (1) Ports P0, P1
50
Ta = -30 C
40
Ta = 25 C
Ta = 95 C
30
IOL [mA]
20
10
0 0.0
0.5
1.0
1.5
2.0
2.5
3.0
VOL [V] (2) Ports P2, RESET pin
50
40
IOL [mA]
30
Ta = -30 C
20
Ta = 25 C Ta = 95 C
10
0 0.0
0.5
1.0
1.5
2.0
2.5
3.0
VOL [V]
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-17
APPENDIX 4506 Group 3.2 Typical characteristics
(3) Ports D0, D1
100 90 80 70 60
Ta = -30 C Ta = 25 C Ta = 95 C
IOL [mA]
50 40 30 20 10 0 0.0
0.5
1.0
1.5
2.0
2.5
3.0
VOL [V] (4) Ports D2/C, D3/K
50
40
30
IOL [mA]
Ta = -30 C Ta = 25 C
20
Ta = 95 C
10
0 0.0
0.5
1.0
1.5
2.0
2.5
3.0
VOL [V]
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-18
APPENDIX 4506 Group 3.2 Typical characteristics
3.2.5 Input threshold (VIH-VIL) characteristics (Ta = 25 C) (1) Ports P0-P2, D2, D3
5.0 4.5 4.0 3.5 3.0
VIHL [V]
2.5 2.0 1.5 1.0 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD [V] (2) Ports D0, D1
5.0 4.5
4.0 3.5
3.0
VIHL [V]
2.5 2.0
1.5 1.0
0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD [V]
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-19
APPENDIX 4506 Group 3.2 Typical characteristics
(3) XIN pin
5.0 4.5
4.0 3.5 3.0
VIHL [V]
2.5
2.0 1.5 1.0
0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD [V] (4) Ports C, K
5.0 4.5 4.0
3.5 3.0 2.5 2.0 1.5
VIHL [V]
1.0 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD [V]
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-20
APPENDIX 4506 Group 3.2 Typical characteristics
(5) RESET pin
6.0 5.5 5.0 4.5 4.0 3.5
VIH
VIH/VIL [V]
3.0
VIL
2.5 2.0 1.5 1.0 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD [V] (6) INT pin, CNTR pin
6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VIH/VIL [V]
VIH VIL
VDD [V]
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-21
APPENDIX 4506 Group 3.2 Typical characteristics
3.2.6 VDD-RPU characteristics (Ports P0-P2, D2/C, D3/K, RESET)
300
250
RPU (k)
200
150
100
Ta = 95 C
50
Ta = 25 C Ta = -30 C
0 2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-22
APPENDIX 4506 Group 3.2 Typical characteristics
3.2.7 Analog input current characteristics pins VAIN-IAIN (VDD = 5 V, high-speed mode, Ta = 25 C) (1) f(XIN) = 4 MHz
200
150
Analog input current IAIN (nA)
100
50
0
-50
-100
-150
-200 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Analog input voltage VAIN (V) (2) f(XIN) = 2 MHz
100 80 60
Analog input current IAIN (nA)
40 20 0 -20 -40
-60 -80 -100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Analog input voltage VAIN (V)
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-23
APPENDIX 4506 Group 3.2 Typical characteristics
(3) f(XIN) = 1 MHz
50 40
30
Analog input current IAIN (nA)
20 10 0
-10 -20 -30
-40 -50 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Analog input voltage VAIN (V)
(4) f(XIN) = 400 kHz
20
15
10
Analog input current IAIN (nA)
5
0
-5
-10
-15
-20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Analog input voltage VAIN (V)
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-24
APPENDIX 4506 Group 3.2 Typical characteristics
3.2.8 Analog input current characteristics pins VAIN-IAIN (VDD = 3 V, high-speed mode, Ta = 25 C) (1) f(XIN) = 4 MHz
100 80 60
Analog input current IAIN (nA)
40 20
0 -20 -40 -60 -80 -100 0.0 0.5 1.0 1.5 2.0 2.5 3.0
Analog input voltage VAIN (V) (2) f(XIN) = 2 MHz
50 40 30
Analog input current IAIN (nA)
20 10 0 -10 -20 -30 -40 -50 0.0 0.5 1.0 1.5 2.0 2.5 3.0
Analog input voltage VAIN (V)
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-25
APPENDIX 4506 Group 3.2 Typical characteristics
(3) f(XIN) = 1 MHz
50 40 30
Analog input current IAIN (nA)
20 10 0 -10 -20 -30 -40 -50 0.0 0.5 1.0 1.5 2.0 2.5 3.0
Analog input voltage VAIN (V)
(4) f(XIN) = 400 kHz
20
15
10
Analog input current IAIN (nA)
5
0
-5
-10
-15
-20 0.0 0.5 1.0 1.5 2.0 2.5 3.0
Analog input voltage VAIN (V)
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-26
APPENDIX 4506 Group 3.2 Typical characteristics
3.2.9 A/D converter operation current (VDD-AIDD) characteristics (Ta = 25 C)
600
500
400
AIDD [A]
300
200
100
0 2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD [V]
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-27
APPENDIX 4506 Group 3.2 Typical characteristics
3.2.10 A/D converter typical characteristics
15 1LSB WIDTH +1LSB
1LSB WIDTH [mV]
ERROR [mV]
0
ERROR
0
-1LSB -15 0
1
1022 1023
Fig. 3.2.1 A/D conversion characteristics data Figure 3.2.1 shows the A/D accuracy measurement data. (1) Non-linearity error ......................... This means a deviation from the ideal characteristics between V0 to V1022 of actual A/D conversion characteristics. In Figure 3.2.1, it is (-)/1LSB. (2) Differencial non-linearity error .... This means a deviation from the ideal characteristics between the input voltages V0 to V1022 necessary to change the output data to "1." In Figure 3.2.1, this is /1LSB. (3) Zero transition error ..................... This means a deviation from the ideal characteristics between the input voltages 0 to VDD when the output data changes from "0" to "1." In Figure 3.2.1, this is the value of . (4) Full-scale transition error ............. This means a deviation from the ideal characteristics between the input voltages 0 to VDD when the output data changes from "1022" to "1023." In Figure 3.2.1, this is the value of . (5) Absolute accuracy ........................ This menas a deviation from the ideal characteristics between 0 to VDD of actual A/D conversion characteristics. In Figure 3.2.1, this is the value of ERROR in each of , and . For the A/D converter characteristics, refer to the section 3.1 Electrical characteristics.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-28
APPENDIX 4506 Group 3.2 Typical characteristics
(1) VDD = 5.12 V, XIN = 4 MHz (high-speed mode), Ta = 25 C
15
ERROR/1LSB WIDTH [mV]
10
Error
5 0 -5
1LSB Width
-10 -15 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
ERROR/1LSB WIDTH [mV]
15 10 5
Error
1LSB Width
0 -5
-10 -15 256
272
288
304
320
336
352
368
384
400
416
432
448
464
480
496
512
ERROR/1LSB WIDTH [mV]
15 10 5 0 -5
Error
1LSB Width
-10 -15 512
528
544
560
576
592
608
624
640
656
672
688
704
720
736
752
768
ERROR/1LSB WIDTH [mV]
15 10 5
Error
1LSB Width
0 -5
-10 -15 768
784
800
816
832
848
864
880
896
912
928
944
960
976
992
1008
1024
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-29
APPENDIX 4506 Group 3.2 Typical characteristics
(2) VDD = 3.072 V, XIN = 2 MHz (high-speed mode), Ta = 25 C
9
ERROR/1LSB WIDTH [mV]
Error
6 3 0
1LSB Width
-3 -6 -9 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
9
ERROR/1LSB WIDTH [mV]
6 3 0
Error
1LSB Width
-3 -6 -9 256
272
288
304
320
336
352
368
384
400
416
432
448
464
480
496
512
ERROR/1LSB WIDTH [mV]
9 6
Error 1LSB Width
3 0
-3 -6 -9 512
528
544
560
576
592
608
624
640
656
672
688
704
720
736
752
768
ERROR/1LSB WIDTH [mV]
9 6
Error 1LSB Width
3 0
-3 -6 -9 768
784
800
816
832
848
864
880
896
912
928
944
960
976
992
1008
1024
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-30
APPENDIX 4506 Group 3.3 List of precautions
3.3 List of precautions
3.3.1 Program counter Make sure that the PCH does not specify after the last page of the built-in ROM. 3.3.2 Stack registers (SKS) Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these operations together. 3.3.3 Notes on I/O port (1) Note when an I/O port is used as an input port Set the output latch to "1" and input the port value before input. If the output latch is set to "0," "L" level can be input. (2) Noise and latch-up prevention Connect an approximate 0.1 F bypass capacitor directly to the VSS line and the VDD line with the thickest possible wire at the shortest distance, and equalize its wiring in width and length. The CNVSS pin is also used as the VPP pin (programming voltage = 12.5 V) at the One Time PROM version. Connect the CNVSS/VPP pin to VSS through an approximate 5 k resistor which is connected to the CNVSS/VPP pin at the shortest distance. (3) Note on multifunction * The input/output of D2, D3, P12 and P13 can be used even when C, K, CNTR (input) and INT are selected. * The input of P12 can be used even when CNTR (output) is selected. * The input/output of P20 and P21 can be used even when AIN0 and AIN1 are selected. (4) Connection of unused pins Table 3.3.1 shows the connections of unused pins. (5) SD, RD instructions When the SD and RD instructions are used, do not set "01002" or more to register Y. (6) Analog input pins When both analog input AIN0 and AIN1 and I/O port P2 function are used, note the following; * Selection of analog input pins Even when P20/AIN0 and P21/AIN1 are set to pins for analog input, they continue to function as port P2 input/output. Accordingly, when any of them are used as I/O port and others are used as analog input pins, make sure to set the outputs of pins that are set for analog input to "1." Also, the port input function of the pin functions as an analog input is undefined. (7) Notes on port P13/INT pin When the bit 3 of register I1 is cleared, the RAM back-up mode is selected and the input of INT pin is disabled, be careful about the following notes. * When the key-on wakeup function of port P13 is not used (register K13 = "0"), clear bits 2 and 3 of register I1 before system enters to the RAM back-up mode.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-31
APPENDIX 4506 Group 3.3 List of precautions
Table 3.3.1 Connections of unused pins Connection Pin Connect to VSS. XIN Open. XOUT
Usage condition System operates by the on-chip oscillator. (Note 1) System operates by the external clock. (The ceramic resonator is selected with the CMCK instruction.) System operates by the RC oscillator. (The RC oscillation is selected with the CRCK instruction.) System operates by the on-chip oscillator. (Note 1)
D0, D1
is set to "1.") The key-on wakeup function is not selected. (Note 4) is set to "0.") The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3) The pull-up function and the key-on wakeup function are not Connect to VSS. selected. (Notes 2, 3) Open. (Output latch is set to "1.") The key-on wakeup function is not selected. (Note 4) P00-P03 Open. (Output latch is set to "0.") The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3) The pull-up function and the key-on wakeup function are not Connect to VSS. selected. (Notes 2, 3) Open. (Output latch is set to "1.") The key-on wakeup function is not selected. (Note 4) P10, P11 P12/CNTR Open. (Output latch is set to "0.") The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3) The pull-up function and the key-on wakeup function are not Connect to VSS. selected. (Notes 2, 3) Open. (Output latch is set to "1.") The key-on wakeup function is not selected. The input to INT P13/INT pin is disabled. (Notes 4, 5) Open. (Output latch is set to "0.") The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3) The pull-up function and the key-on wakeup function are not Connect to VSS. selected. (Notes 2, 3) Open. (Output latch is set to "1.") The key-on wakeup function is not selected. (Note 4) P20/AIN0 Open. (Output latch is set to "0.") The pull-up function and the key-on wakeup function are not P21/AIN1 selected. (Notes 2, 3) The pull-up function and the key-on wakeup function are not Connect to VSS. selected. (Notes 2, 3) Notes 1: When the ceramic resonator or the RC oscillation is not selected by program, system operates by the on-chip oscillator (internal oscillator). 2: When the pull-up function is left valid, the supply current is increased. Do not select the pull-up function. 3: When the key-on wakeup function is left valid, the system returns from the RAM back-up state immediately after going into the RAM back-up state. Do not select the key-on wakeup function. 4: When selecting the key-on wakeup function, select also the pull-up function. 5: Clear the bit 3 (I13) of register I1 to "0" to disable to input to INT pin (after reset: I13 = "0") D2/C D3/K (Note when connecting to VSS) q Connect the unused pins to VSS using the thickest wire at the shortest distance against noise.
Open. (Output latch Open. (Output latch Connect to VSS. Open. (Output latch Open. (Output latch
is set to "1.") is set to "0.")
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-32
APPENDIX 4506 Group 3.3 List of precautions
3.3.4 Notes on interrupt (1) Setting of INT interrupt valid waveform Set a value to the bit 2 of register I1, and execute the SNZ0 instruction to clear the EXF0 flag to "0" after executing at least one instruction. Depending on the input state of P13/INT pin, the external interrupt request flag (EXF0) may be set to "1" when the interrupt valid waveform is changed. (2) Setting of INT pin input control Set a value to the bit 3 of register I1, and execute the SNZ0 instruction to clear the EXF0 flag to "0" after executing at least one instruction. Depending on the input state of P13/INT pin, the external interrupt request flag (EXF0) may be set to "1" when the interrupt valid waveform is changed. (3) Multiple interrupts Multiple interrupts cannot be used in the 4506 Group. (4) Notes on interrupt processing When the interrupt occurs, at the same time, the interrupt enable flag INTE is cleared to "0" (interrupt disable state). In order to enable the interrupt at the same time when system returns from the interrupt, write EI and RTI instructions continuously. (5) P13/INT pin Note [1] on bit 3 of register I1 When the input of the INT pin is controlled with the bit 3 of register I1 in software, be careful about the following notes. * Depending on the input state of the P13/INT pin, the external 0 interrupt request flag (EXF0) may be set when the bit 3 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to "0" (refer to Figure 3.3.1 ) and then, change the bit 3 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to "0" after executing at least one instruction (refer to Figure 3.3.1 ). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 3.3.1 ).
LA TV1A LA TI1A NOP SNZ0 NOP
***
4 ; (02) ; The SNZ0 instruction is valid ..... 8 ; (12) ; Control of INT pin input is changed ; .......................................................... ; The SNZ0 instruction is executed (EXF0 flag cleared) ; ..........................................................
***
: these bits are not used here. Fig. 3.3.1 External 0 interrupt program example-1
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-33
APPENDIX 4506 Group 3.3 List of precautions
Note [2] on bit 3 of register I1 When the bit 3 of register I1 is cleared to "0", the RAM back-up mode is selected and the input of INT pin is disabled, be careful about the following notes. * When the key-on wakeup function of port P13 is not used (register K13 = "0"), clear bits 2 and 3 of register I1 before system enters to the RAM back-up mode. (refer to Figure 3.3.2 ).
LA TI1A DI EPOF POF2
***
0 ; (002) ; Input of INT disabled .................... ; RAM back-up : these bits are not used here. Fig. 3.3.2 External 0 interrupt program example-2 Note [3] on bit 2 of register I1 When the interrupt valid waveform of the P13/INT pin is changed with the bit 2 of register I1 in software, be careful about the following notes. * Depending on the input state of the P13/INT pin, the external 0 interrupt request flag (EXF0) may be set when the bit 2 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to "0" (refer to Figure 3.3.3 ) and then, change the bit 2 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to "0" after executing at least one instruction (refer to Figure 3.3.3 ). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 3.3.3 ).
***
LA 4 TV1A LA 12 TI1A NOP SNZ0 NOP
***
***
; (02) ; The SNZ0 instruction is valid ..... ; (12) ; Interrupt valid waveform is changed ........................................................... ; The SNZ0 instruction is executed (EXF0 flag cleared) ........................................................... : these bits are not used here. Fig. 3.3.3 External 0 interrupt program example-3 (6) Power down instruction Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-34
APPENDIX 4506 Group 3.3 List of precautions
3.3.5 Notes on timer (1) Prescaler Stop the prescaler operation to change its frequency dividing ratio. (2) Count source Stop timer 1 or 2 counting to change its count source. (3) Reading the count values Stop timer 1 or 2 counting and then execute the TAB1 or TAB2 instruction to read its data. (4) Writing to the timer Stop timer 1 or 2 counting and then execute the T1AB or T2AB instruction to write its data. (5) Writing to reload register R1 When writing data to reload register R1 while timer 1 is operating, avoid a timing when timer 1 underflow. (6) Timer 1 and timer 2 count start timing and count time when operation starts Count starts from the first rising edge of the count source (2) after timer 1 and timer 2 operations start (1). Time to first underflow (3) is shorter (for up to 1 period of the count source) than time among next underflow (4) by the timing to start the timer and count source operations after count starts. When selecting CNTR input as the count source of timer 2, timer 2 operates synchronizing with the falling edge of CNTR input.
(2) Count Source Count Source (CNTR input) Timer Value 3 2 1 0 3 2 1 0 3 2
Timer Underflow Signal (3) (1) Timer (4)
Fig. 3.3.4
Timer count start timing and count time when operation starts (T1, T2)
(7) Watchdog timer * The watchdog timer function is valid after system is released from reset. When not using the watchdog timer function, execute the DWDT instruction and the WRST instruction continuously, and clear the WEF flag to "0" to stop the watchdog timer function. * The watchdog timer function is valid after system is returned from the RAM back-up. When not using the watchdog timer function, execute the DWDT instruction and the WRST instruction continuously every system is returned from the RAM back-up, and stop the watchdog timer function. (8) Pulse width input to CNTR pin Table 3.3.2 shows the recommended operating condition of pulse width input to CNTR pin. Table 3.3.2 Recommended operating condition of pulse width input to CNTR pin Parameter Timer external input period ("H" and "L" pulse width) Condition High-speed mode Middle-speed mode Low-speed mode Default mode
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
Min. 3/f(XIN) 6/f(XIN) 12/f(XIN) 24/f(XIN)
Rating value Typ.
Max.
Unit
s
3-35
APPENDIX 4506 Group 3.3 List of precautions
3.3.6 Notes on A/D conversion (1) Note when the A/D conversion starts again When the A/D conversion starts again with the ADST instruction during A/D conversion, the previous input data is invalidated and the A/D conversion starts again. (2) A/D converter-1 Each analog input pin is equipped with a capacitor which is used to compare the analog voltage. Accordingly, when the analog voltage is input from the circuit with high-impedance and, charge/ discharge noise is generated and the sufficient A/D accuracy may not be obtained. Therefore, reduce the impedance or, connect a capacitor (0.01 F to 1 F) to analog input pins. Figure 3.3.5 shows the analog input external circuit example-1. When the overvoltage applied to the A/D conversion circuit may occur, connect an external circuit in order to keep the voltage within the rated range as shown the Figure 3.3.6 In addition, test the application products sufficiently.
Sensor
AIN (Note)
About 1 k
Sensor
AIN
Note: Apply the voltage within the specifications to an analog input pin.
Fig. 3.3.6 Analog input external circuit example-2 Fig. 3.3.5 Analog input external circuit example-1 (3) Notes for the use of A/D conversion 2 When the operating mode of the A/D converter is changed from the comparator mode to the A/D conversion mode with bit 3 of register Q1 in a program, be careful about the following notes. * Clear bit 2 of register V2 to "0" to change the operating mode of the A/D converter from the comparator mode to the A/D conversion mode with bit 3 of register Q1 (refer to Figure 3.3.7). * The A/D conversion completion flag (ADF) may be set when the operating mode of the A/D converter is changed from the comparator mode to the A/D conversion mode. Accordingly, set a value to bit 3 of register Q1, and execute the SNZAD instruction to clear the ADF flag. Do not change the operating mode (both A/D conversion mode and comparator mode) of A/D converter with bit 3 of register Q1 during operating the A/D converter. * * * Clear bit 2 of register V2 to "0"....... Change of the operating mode of the A/D converter from the comparator mode to the A/D conversion mode Clear the ADF flag to "0" with the SNZAD instruction Execute the NOP instruction for the case when a skip is performed with the SNZAD instruction * * * Fig. 3.3.7 A/D converter operating mode program example
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-36
APPENDIX 4506 Group 3.3 List of precautions
(4) A/D converter is used at the comparator mode The analog input voltage is higher than the comparison voltage as a result of comparison, the contents of ADF flag retains "0," not set to "1." In this case, the A/D interrupt does not occur even when the usage of the A/D interrupt is enabled. Accordingly, consider the time until the comparator operation is completed, and examine the state of ADF flag by software. The comparator operation is completed after 8 machine cycles. (5) Analog input pins Even when P20/AIN0 and P21/AIN1 are set to pins for analog input, they continue to function as P2 I/O. Accordingly, when any of them are used as these ports and others are used as analog input pins, make sure to set the outputs of pins that are set for analog input to "1." Also, the port input function of the pin functions as an analog input is undefined. (6) TALA instruction When the TALA instruction is executed, the low-order 2 bits of register AD is transferred to the highorder 2 bits of register A, and simultaneously, the low-order 2 bits of register A is "0." (7) Recommended operating conditions when using A/D converter The recommended operating conditions of supply voltage and system clock frequency when using A/ D converter are different from those when not using A/D converter. Table 3.3.3 shows the recommended operating conditions when using A/D converter. Table 3.3.3 Recommended operating conditions (when using A/D converter) Parameter Condition Limits Unit Min. Typ. Max. 0.1 4.4 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 Duty 40 % to 60 % 0.1 0.1 2.2 1.1 0.5 4.4 2.2 1.1 0.5 3.2 1.6 0.8 0.4 MHz
System clock frequency VDD = 2.7 to 5.5 V (high-speed mode) (at ceramic resonance) VDD = 2.7 to 5.5 V (middle-speed mode) VDD = 2.7 to 5.5 V (low-speed mode) VDD = 2.7 to 5.5 V (default mode) System clock frequency VDD = 2.7 to 5.5 V (high-speed mode) (at RC oscillation) (Note) VDD = 2.7 to 5.5 V (middle-speed mode) VDD = 2.7 to 5.5 V (low-speed mode) VDD = 2.7 System clock frequency VDD = 2.7 ( c e r a m i c r e s o n a n c e VDD = 2.7 selected, at external VDD = 2.7 clock input) VDD = 2.7 to 5.5 V (default mode) to 5.5 V (high-speed mode) to 5.5 V (middle-speed mode) to 5.5 V (low-speed mode) to 5.5 V (default mode)
Note: The frequency at RC oscillation is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits. 3.3.7 Notes on reset (1) Register initial value The initial value of the following registers are undefined after system is released from reset. After system is released from reset, set initial values. * Register Z (2 bits) * Register D (3 bits) * Register E (8 bits)
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-37
APPENDIX 4506 Group 3.3 List of precautions
3.3.8 Notes on RAM back-up (1) Key-on wakeup function After setting ports (P0, P1, D2/C, D3/K, P20/AIN0 and P21/AIN1 specified with register K0-K2) which keyon wakeup function is valid to "H," execute the POF2 instruction. If one of ports which key-on wakeup function is valid is in the "L" level state, system returns from the RAM back-up after the POF2 instruction is executed. (2) POF2 instruction Execute the POF2 instruction immediately after executing the EPOF instruction to enter the RAM back-up state. Note that system cannot enter the RAM back-up state when executing only the POF2 instruction. Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction and the POF2 instruction. (3) Return from RAM back-up After system returns from RAM back-up, set the undefined registers and flags. The initial value of the following registers are undefined at RAM back-up. After system is returned from RAM back-up, set initial values. * Register Z (2 bits) * Register X (4 bits) * Register Y (4 bits) * Register D (3 bits) * Register E (8 bits) (4) Watchdog timer The watchdog timer function is valid after system is returned from the RAM back-up. When not using the watchdog timer function, execute the DWDT instruction and the WRST instruction continuously every system is returned from the RAM back-up, and stop the watchdog timer function. (5) P13/INT pin When the bit 3 of register I1 is cleared, the RAM back-up mode is selected and the input of INT pin is disabled, be careful about the following notes. * When the key-on wakeup function of port P13 is not used (register K13 = "0"), clear bits 2 and 3 of register I1 before system enters to the RAM back-up mode. (6) External clock When the external signal clock is used as the source oscillation (f(XIN)), note that the RAM back-up mode (POF2 instruction) cannot be used.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-38
APPENDIX 4506 Group 3.3 List of precautions
3.3.9 Notes on oscillation control (1) Clock control Execute the CMCK or the CRCK instruction in the initial setting routine of program (executing it in address 0 in page 0 is recommended). The oscillation circuit by the CMCK or CRCK instruction can be selected only at once. The oscillation circuit corresponding to the first executed one of these two instructions is valid. Other oscillation circuits and the on-chip oscillator stop. (2) On-chip oscillator The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that variable frequencies when designing application products. Also, the oscillation stabilize wait time after system is released from reset is generated by the onchip oscillator clock. When considering the oscillation stabilize wait time after system is released from reset, be careful that the variable frequency of the on-chip oscillator clock. (3) External clock When the external signal clock is used as the source oscillation (f(XIN)), note that the RAM back-up mode (POF2 instruction) cannot be used. (4) Value of a part connected to an oscillator Values of a capacitor and a resistor of the oscillation circuit depend on the connected oscillator and the board. Accordingly, consult the oscillator manufacturer for values of each part connected the oscillator. 3.3.10 Electric Characteristic Differences Between Mask ROM and One Time PROM Version MCU There are differences in electric characteristics, operation margin, noise immunity, and noise radiation between Mask ROM and One Time PROM version MCUs due to the difference in the manufacturing processes. When manufacturing an application system with the One time PROM version and then switching to use of the Mask ROM version, please perform sufficient evaluations for the commercial samples of the Mask ROM version. 3.3.11 Note on Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the supply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation.
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-39
APPENDIX 4506 Group 3.4 Notes on noise
3.4 Notes on noise
Countermeasures against noise are described below. The following countermeasures are effective against noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use. 3.4.1 Shortest wiring length The wiring on a printed circuit board can function as an antenna which feeds noise into the microcomputer. The shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer. (1) Package Select the smallest possible package to make the total wiring length short. q Reason The wiring length depends on a microcomputer package. Use of a small package, for example QFP and not DIP, makes the total wiring length short to reduce influence of noise.
(2) Wiring for RESET input pin Make the length of wiring which is connected to the RESET input pin as short as possible. Especially, connect a capacitor across the RESET input pin and the VSS pin with the shortest possible wiring. q Reason In order to reset a microcomputer correctly, 1 machine cycle or more of the width of a pulse input into the RESET pin is required. If noise having a shorter pulse width than this is input to the RESET input pin, the reset is released before the internal state of the microcomputer is completely initialized. This may cause a program runaway.
Noise
Reset circuit VSS
N.G.
RESET VSS
DIP SDIP SOP QFP
O.K.
Reset circuit VSS
RESET VSS
Fig. 3.4.2 Wiring for the RESET input pin Fig. 3.4.1 Selection of packages
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-40
APPENDIX 4506 Group 3.4 Notes on noise
(3) Wiring for clock input/output pins * Make the length of wiring which is connected to clock I/O pins as short as possible. * Make the length of wiring across the grounding lead of a capacitor which is connected to an oscillator and the VSS pin of a microcomputer as short as possible. * Separate the VSS pattern only for oscillation from other VSS patterns.
(4) Wiring to CNVSS pin Connect the CNVSS pin to the VSS pin with the shortest possible wiring. q Reason The operation mode of a microcomputer is influenced by a potential at the CNVSS pin. If a potential difference is caused by the noise between pins CNVSS and VSS, the operation mode may become unstable. This may cause a microcomputer malfunction or a program runaway.
Noise
Noise
XIN XOUT VSS
N.G.
XIN XOUT VSS
O.K.
CNVSS VSS
CNVSS VSS
Fig. 3.4.3 Wiring for clock I/O pins q Reason If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program failure or program runaway. Also, if a potential difference is caused by the noise between the VSS level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in the microcomputer.
N.G.
O.K.
Fig. 3.4.4 Wiring for CNVSS pin
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-41
APPENDIX 4506 Group 3.4 Notes on noise
(5) Wiring to VPP pin of built-in PROM version In the built-in PROM version of the 4506 Group, the CNVSS pin is also used as the built-in PROM power supply input pin VPP. q When the VPP pin is also used as the CNVSS pin Connect an approximately 5 k resistor to the VPP pin the shortest possible in series and also to the VSS pin. When not connecting the resistor, make the length of wiring between the VPP pin and the VSS pin the shortest possible (refer to Figure 3.4.5) Note: Even when a circuit which included an approximately 5 k resistor is used in the Mask ROM version, the microcomputer operates correctly. q Reason The VPP pin of the built-in PROM version is the power source input pin for the builtin PROM. When programming in the builtin PROM, the impedance of the VPP pin is low to allow the electric current for writing flow into the PROM. Because of this, noise can enter easily. If noise enters the VPP pin, abnormal instruction codes or data are read from the built-in PROM, which may cause a program runaway.
When the VPP pin is also used as the CNVSS pin Approximately 5k CNVSS/VPP VSS
3.4.2 Connection of bypass capacitor across VSS line and VDD line Connect an approximately 0.1 F bypass capacitor across the VSS line and the VDD line as follows: * Connect a bypass capacitor across the VSS pin and the VDD pin at equal length. * Connect a bypass capacitor across the VSS pin and the VDD pin with the shortest possible wiring. * Use lines with a larger diameter than other signal lines for VSS line and VDD line. * Connect the power source wiring via a bypass capacitor to the VSS pin and the VDD pin.
VDD
VDD
VSS
VSS
N.G.
O.K.
Fig. 3.4.6 Bypass capacitor across the VSS line and the VDD line
In the shortest distance
Fig. 3.4.5 Wiring for the VPP pin of the built-in PROM version
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-42
APPENDIX 4506 Group 3.4 Notes on noise
3.4.3 Wiring to analog input pins * Connect an approximately 100 to 1 k resistor to an analog signal line which is connected to an analog input pin in series. Besides, connect the resistor to the microcomputer as close as possible. * Connect an approximately 1000 pF capacitor across the VSS pin and the analog input pin. Besides, connect the capacitor to the VSS pin as close as possible. Also, connect the capacitor across the analog input pin and the VSS pin at equal length. q Reason Signals which is input in an analog input pin (such as an A/D converter/comparator input pin) are usually output signals from sensor. The sensor which detects a change of event is installed far from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer necessarily. This long wiring functions as an antenna which feeds noise into the microcomputer, which causes noise to an analog input pin.
3.4.4 Oscillator concerns Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. (1) Keeping oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. q Reason In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise occurs because of mutual inductance.
Microcomputer Mutual inductance M
Noise
(Note)
Microcomputer Analog input pin
N.G. O.K.
Large current GND
XIN XOUT VSS
Thermistor
Fig. 3.4.8 Wiring for a large current signal line
VSS
Note : The resistor is used for dividing resistance with a thermistor.
Fig. 3.4.7 Analog signal line and a resistor and a capacitor
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-43
APPENDIX 4506 Group 3.4 Notes on noise
(2) Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. q Reason Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway.
3.4.5 Setup for I/O ports Setup I/O ports using hardware and software as follows: * Connect a resistor of 100 or more to an I/O port in series. * As for an input port, read data several times by a program for checking whether input levels are equal or not. * As for an output port or an I/O port, since the output data may reverse because of noise, rewrite data to its output latch at fixed periods. * Rewrite data to pull-up control registers at fixed periods. 3.4.6 Providing of watchdog timer function by software If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. This is equal to or more effective than program runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer provided by software. In the following example, to reset a microcomputer to normal operation, the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine. This example assumes that interrupt processing is repeated multiple times in a single main routine processing.
N.G.
Do not cross
CNTR XIN XOUT VSS
Fig. 3.4.9 Wiring to a signal line where potential levels change frequently (3) Oscillator protection using VSS pattern As for a two-sided printed circuit board, print a VSS pattern on the underside (soldering side) of the position (on the component side) where an oscillator is mounted. Connect the VSS pattern to the microcomputer VSS pin with the shortest possible wiring. Besides, separate this VSS pattern from other VSS patterns.
An example of VSS patterns on the underside of a printed circuit board Oscillator wiring pattern example
XIN XOUT VSS
Separate the VSS line for oscillation from other VSS lines
Fig. 3.4.10 VSS pattern on the underside of an oscillator
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-44
APPENDIX 4506 Group 3.4 Notes on noise
* Assigns a single word of RAM to a software watchdog timer (SWDT) and writes the initial value N in the SWDT once at each execution of the main routine. The initial value N should satisfy the following condition: N+1 (Counts of interrupt processing executed in each main routine)
As the main routine execution cycle may change because of an interrupt processing or others, the initial value N should have a margin. * Watches the operation of the interrupt processing routine by comparing the SWDT contents with counts of interrupt processing after the initial value N has been set. * Detects that the interrupt processing routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: If the SWDT contents do not change after interrupt processing. * Decrements the SWDT contents by 1 at each interrupt processing. * Determines that the main routine operates normally when the SWDT contents are reset to the initial value N at almost fixed cycles (at the fixed interrupt processing count). * Detects that the main routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: If the SWDT contents are not initialized to the initial value N but continued to decrement and if they reach 0 or less.
Main routine (SWDT) N EI Main processing N (SWDT) =N? N Interrupt processing routine (SWDT) (SWDT)--1 Interrupt processing (SWDT) 0? 0 >0 RTI Return Main routine errors
Interrupt processing routine errors
Fig. 3.4.11 Watchdog timer by software
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-45
APPENDIX 4506 Group 3.5 Package outline
3.5 Package outline
JEITA Package Code P-SOP20-5.3x12.6-1.27 RENESAS Code PRSP0020DA-A Previous Code 20P2N-A MASS[Typ.] 0.3g
20 11
HE
*1
E
F
1 Index mark *2 D
10
NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
c
A2
A1
Reference Symbol
Dimension in Millimeters Min 12.5 5.2 Nom 12.6 5.3 1.8 0 0.1 0.2 2.1 0.35 0.18 0 0.4 0.2 0.5 0.25 8 7.8 1.27 8.1 1.42 0.1 0.4 0.6 0.8 Max 12.7 5.4
A
D
L
E A2
*3 e bp y Detail F
A1 A bp c
HE e y L
7.5 1.12
Rev.2.01 Feb 07, 2005 REJ09B0194-0201
3-46
RENESAS 4-BIT CISC SINGLE-CHIP MICROCOMPUTER USER'S MANUAL 4506 Group Publication Data : Rev.1.00 Nov 29, 2002 Rev.2.01 Feb 07, 2005 Sales Strategic Planning Div. Renesas Technology Corp.
Published by :
(c) 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
4506 Group User's Manual
2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan

▲Up To Search▲

Price & Availability of 4506

	To Download 4506 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .